6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-21 02:24:22 +00:00
Code Issues Projects Releases Wiki Activity

Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Barton
2012-04-27 08:42:59 +00:00
parent d213ee7643
commit 4d2f077df1
3 changed files with 7 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -63,7 +63,7 @@ namespace {
// fields in the IT instruction encoding.
void setITState(char Firstcond, char Mask) {
// (3 - the number of trailing zeros) is the number of then / else.
unsigned CondBit0 = Mask >> 4 & 1;
unsigned CondBit0 = Firstcond & 1;
unsigned NumTZ = CountTrailingZeros_32(Mask);
unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
assert(NumTZ <= 3 && "Invalid IT mask!");
@ -4217,19 +4217,14 @@ static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
DecodeStatus S = MCDisassembler::Success;
unsigned pred = fieldFromInstruction16(Insn, 4, 4);
// The InstPrinter needs to have the low bit of the predicate in
// the mask operand to be able to print it properly.
unsigned mask = fieldFromInstruction16(Insn, 0, 5);
unsigned mask = fieldFromInstruction16(Insn, 0, 4);
if (pred == 0xF) {
pred = 0xE;
S = MCDisassembler::SoftFail;
}
if ((mask & 0xF) == 0) {
// Preserve the high bit of the mask, which is the low bit of
// the predicate.
mask &= 0x10;
if (mask == 0x0) {
mask |= 0x8;
S = MCDisassembler::SoftFail;
}