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Fix a typo in the dag combiner, so that this can work on i64 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23856 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2607,9 +2607,8 @@ SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
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}
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// Extract the sign bit and add it to the quotient
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SDOperand T =
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DAG.getNode(ISD::SRL, MVT::i32, Q,
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DAG.getConstant(MVT::getSizeInBits(VT)-1,
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TLI.getShiftAmountTy()));
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DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
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TLI.getShiftAmountTy()));
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WorkList.push_back(T.Val);
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return DAG.getNode(ISD::ADD, VT, Q, T);
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}
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