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Swap fp comparison operands and change predicate to allow load folding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1909,7 +1909,6 @@ SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
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}
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}
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/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
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/// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
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/// specific condition code. It returns a false if it cannot do a direct
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/// specific condition code. It returns a false if it cannot do a direct
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/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
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/// translation. X86CC is the translated CondCode. LHS/RHS are modified as
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@ -1936,7 +1935,10 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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return true;
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return true;
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}
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}
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}
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}
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}
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bool Flip = false;
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if (!isFP) {
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switch (SetCCOpcode) {
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switch (SetCCOpcode) {
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default: break;
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default: break;
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case ISD::SETEQ: X86CC = X86::COND_E; break;
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case ISD::SETEQ: X86CC = X86::COND_E; break;
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@ -1957,7 +1959,6 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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// 0 | 0 | 1 | X < Y
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// 0 | 0 | 1 | X < Y
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// 1 | 0 | 0 | X == Y
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// 1 | 0 | 0 | X == Y
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// 1 | 1 | 1 | unordered
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// 1 | 1 | 1 | unordered
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bool Flip = false;
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switch (SetCCOpcode) {
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switch (SetCCOpcode) {
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default: break;
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default: break;
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case ISD::SETUEQ:
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case ISD::SETUEQ:
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@ -1979,11 +1980,24 @@ static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
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case ISD::SETUO: X86CC = X86::COND_P; break;
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case ISD::SETUO: X86CC = X86::COND_P; break;
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case ISD::SETO: X86CC = X86::COND_NP; break;
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case ISD::SETO: X86CC = X86::COND_NP; break;
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}
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}
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if (Flip)
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std::swap(LHS, RHS);
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}
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}
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return X86CC != X86::COND_INVALID;
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if (X86CC == X86::COND_INVALID)
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return false;
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if (Flip)
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std::swap(LHS, RHS);
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if (isFP) {
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bool LHSCanFold = ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse();
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bool RHSCanFold = ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse();
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if (LHSCanFold && !RHSCanFold) {
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X86CC = X86::GetSwappedBranchCondition(static_cast<X86::CondCode>(X86CC));
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std::swap(LHS, RHS);
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}
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}
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return true;
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}
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}
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/// hasFPCMov - is there a floating point cmov for the specific X86 condition
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/// hasFPCMov - is there a floating point cmov for the specific X86 condition
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@ -1433,6 +1433,30 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
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}
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}
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}
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}
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/// GetSwappedBranchCondition - Return the branch condition that would be
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/// the result of exchanging the two operands of a comparison without
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/// changing the result produced.
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/// e.g. COND_E to COND_E, COND_G -> COND_L
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X86::CondCode X86::GetSwappedBranchCondition(X86::CondCode CC) {
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case X86::COND_E: return X86::COND_E;
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case X86::COND_NE: return X86::COND_NE;
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case X86::COND_L: return X86::COND_G;
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case X86::COND_LE: return X86::COND_GE;
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case X86::COND_G: return X86::COND_L;
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case X86::COND_GE: return X86::COND_LE;
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case X86::COND_B: return X86::COND_A;
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case X86::COND_BE: return X86::COND_AE;
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case X86::COND_A: return X86::COND_B;
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case X86::COND_AE: return X86::COND_BE;
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case X86::COND_P: return X86::COND_P;
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case X86::COND_NP: return X86::COND_NP;
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case X86::COND_O: return X86::COND_O;
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case X86::COND_NO: return X86::COND_NO;
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}
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}
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bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isTerminator()) return false;
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if (!TID.isTerminator()) return false;
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@ -2373,7 +2397,8 @@ bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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bool X86InstrInfo::
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bool X86InstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid X86 branch condition!");
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assert(Cond.size() == 1 && "Invalid X86 branch condition!");
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Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm()));
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X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
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Cond[0].setImm(GetOppositeBranchCondition(CC));
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return false;
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return false;
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}
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}
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@ -54,6 +54,11 @@ namespace X86 {
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/// e.g. turning COND_E to COND_NE.
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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/// GetSwappedBranchCondition - Return the branch condition that would be
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/// the result of exchanging the two operands of a comparison without
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/// changing the result produced.
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/// e.g. COND_E to COND_E, COND_G -> COND_L
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CondCode GetSwappedBranchCondition(X86::CondCode CC);
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}
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}
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/// X86II - This namespace holds all of the target specific flags that
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/// X86II - This namespace holds all of the target specific flags that
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18
test/CodeGen/X86/cmp2.ll
Normal file
18
test/CodeGen/X86/cmp2.ll
Normal file
@ -0,0 +1,18 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep ucomisd | grep CPI | count 2
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define i32 @test(double %A) nounwind {
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entry:
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%tmp2 = fcmp ogt double %A, 1.500000e+02; <i1> [#uses=1]
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%tmp5 = fcmp olt double %A, 7.500000e+01; <i1> [#uses=1]
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%bothcond = or i1 %tmp2, %tmp5; <i1> [#uses=1]
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br i1 %bothcond, label %bb8, label %bb12
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bb8:; preds = %entry
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%tmp9 = tail call i32 (...)* @foo( ) nounwind ; <i32> [#uses=1]
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ret i32 %tmp9
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bb12:; preds = %entry
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ret i32 32
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}
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declare i32 @foo(...)
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@ -2,17 +2,17 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep shr | count 1
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; RUN: llvm-as < %s | llc -march=x86 | grep shr | count 1
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; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 1
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; RUN: llvm-as < %s | llc -march=x86 | grep xor | count 1
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define i1 @t1(i64 %x) {
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define i1 @t1(i64 %x) nounwind {
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%B = icmp slt i64 %x, 0
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%B = icmp slt i64 %x, 0
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ret i1 %B
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ret i1 %B
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}
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}
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define i1 @t2(i64 %x) {
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define i1 @t2(i64 %x) nounwind {
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%tmp = icmp ult i64 %x, 4294967296
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%tmp = icmp ult i64 %x, 4294967296
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ret i1 %tmp
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ret i1 %tmp
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}
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}
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define i1 @t3(i32 %x) {
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define i1 @t3(i32 %x) nounwind {
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%tmp = icmp ugt i32 %x, -1
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%tmp = icmp ugt i32 %x, -1
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ret i1 %tmp
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ret i1 %tmp
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}
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}
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