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Add definitions of 32/64-bit unaligned load/store instructions for Mips.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157865 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-06-02 00:04:19 +00:00
parent 1cd0ec007a
commit 4d70ceed33
2 changed files with 70 additions and 27 deletions
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12
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -141,6 +141,18 @@ defm USW64 : StoreM64<0x2b, "usw", truncstorei32_u, 1>;
defm ULD : LoadM64<0x37, "uld", load_u, 1>;
defm USD : StoreM64<0x3f, "usd", store_u, 1>;
/// load/store left/right
let isCodeGenOnly = 1 in {
defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>;
defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>;
defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>;
defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>;
}
defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>;
defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>;
defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>;
defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>;
/// Load-linked, Store-conditional
def LLD : LLBase<0x34, "lld", CPU64Regs, mem>,
Requires<[NotN64, HasStandardEncoding]>;

85
lib/Target/Mips/MipsInstrInfo.td
View File

@ -445,14 +445,6 @@ class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
let isPseudo = Pseudo;
}
// Unaligned Memory Load/Store
let canFoldAsLoad = 1 in
class LoadUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), "", [], IILoad> {}
class StoreUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), "", [], IIStore> {}
// 32-bit load.
multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
bit Pseudo = 0> {
@ -477,16 +469,6 @@ multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
}
}
// 32-bit load.
multiclass LoadUnAlign32<bits<6> op> {
def #NAME# : LoadUnAlign<op, CPURegs, mem>,
Requires<[NotN64, HasStandardEncoding]>;
def _P8 : LoadUnAlign<op, CPURegs, mem64>,
Requires<[IsN64, HasStandardEncoding]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 32-bit store.
multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
bit Pseudo = 0> {
@ -511,11 +493,60 @@ multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
}
}
// 32-bit store.
multiclass StoreUnAlign32<bits<6> op> {
def #NAME# : StoreUnAlign<op, CPURegs, mem>,
// Load/Store Left/Right
let canFoldAsLoad = 1 in
class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
RegisterClass RC, Operand MemOpnd> :
FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
!strconcat(instr_asm, "\t$rt, $addr"),
[(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
string Constraints = "$src = $rt";
}
class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
RegisterClass RC, Operand MemOpnd>:
FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
!strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
IIStore>;
// 32-bit load left/right.
multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
Requires<[NotN64, HasStandardEncoding]>;
def _P8 : StoreUnAlign<op, CPURegs, mem64>,
def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
Requires<[IsN64, HasStandardEncoding]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 64-bit load left/right.
multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
Requires<[NotN64, HasStandardEncoding]>;
def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
Requires<[IsN64, HasStandardEncoding]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 32-bit store left/right.
multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
Requires<[NotN64, HasStandardEncoding]>;
def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
Requires<[IsN64, HasStandardEncoding]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
// 64-bit store left/right.
multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
Requires<[NotN64, HasStandardEncoding]>;
def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
Requires<[IsN64, HasStandardEncoding]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
@ -907,11 +938,11 @@ defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
defm USW : StoreM32<0x2b, "usw", store_u, 1>;
/// Primitives for unaligned
defm LWL : LoadUnAlign32<0x22>;
defm LWR : LoadUnAlign32<0x26>;
defm SWL : StoreUnAlign32<0x2A>;
defm SWR : StoreUnAlign32<0x2E>;
/// load/store left/right
defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
let hasSideEffects = 1 in
def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",