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[X86] Improve mul w/ overflow codegen, to MUL8+SETO.
Currently, @llvm.smul.with.overflow.i8 expands to 9 instructions, where 3 are really needed. This adds X86ISD::UMUL8/SMUL8 SD nodes, and custom lowers them to MUL8/IMUL8 + SETO. i8 is a special case because there is no two/three operand variants of (I)MUL8, so the first operand and return value need to go in AL/AX. Also, we can't write patterns for these instructions: TableGen refuses patterns where output operands don't match SDNode results. In this case, instructions where the output operand is an implicitly defined register. A related special case (and FIXME) exists for MUL8 (X86InstrArith.td): // FIXME: Used for 8-bit mul, ignore result upper 8 bits. // This probably ought to be moved to a def : Pat<> if the // syntax can be accepted. [(set AL, (mul AL, GR8:$src)), (implicit EFLAGS)] Ideally, these go away with UMUL8, but we still need to improve TableGen support of implicit operands in patterns. Before this change: movsbl %sil, %eax movsbl %dil, %ecx imull %eax, %ecx movb %cl, %al sarb $7, %al movzbl %al, %eax movzbl %ch, %esi cmpl %eax, %esi setne %al After: movb %dil, %al imulb %sil seto %al Also, remove a made-redundant testcase for PR19858, and enable more FastISel ALU-overflow tests for SelectionDAG too. Differential Revision: http://reviews.llvm.org/D5809 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220516 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2218,6 +2218,25 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
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return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
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getI8Imm(ShlVal));
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}
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case X86ISD::UMUL8:
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case X86ISD::SMUL8: {
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
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SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
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N0, SDValue()).getValue(1);
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SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
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SDValue Ops[] = {N1, InFlag};
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SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
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ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
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ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
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return nullptr;
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}
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case X86ISD::UMUL: {
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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@ -1597,9 +1597,6 @@ void X86TargetLowering::resetOperationActions() {
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setOperationAction(ISD::UMULO, VT, Custom);
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}
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// There are no 8-bit 3-address imul/mul instructions
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setOperationAction(ISD::SMULO, MVT::i8, Expand);
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setOperationAction(ISD::UMULO, MVT::i8, Expand);
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if (!Subtarget->is64Bit()) {
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// These libcalls are not available in 32-bit.
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@ -18190,10 +18187,15 @@ static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
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Cond = X86::COND_B;
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break;
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case ISD::SMULO:
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BaseOp = X86ISD::SMUL;
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BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
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Cond = X86::COND_O;
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break;
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case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
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if (N->getValueType(0) == MVT::i8) {
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BaseOp = X86ISD::UMUL8;
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Cond = X86::COND_O;
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break;
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}
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SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
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MVT::i32);
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SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
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@ -301,6 +301,9 @@ namespace llvm {
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UMUL, // LOW, HI, FLAGS = umul LHS, RHS
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// 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS
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SMUL8, UMUL8,
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// MUL_IMM - X86 specific multiply by immediate.
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MUL_IMM,
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@ -1,24 +0,0 @@
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; RUN: llc -mcpu=generic -march=x86 < %s | FileCheck %s
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; PR19858
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declare {i8, i1} @llvm.umul.with.overflow.i8(i8 %a, i8 %b)
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define i8 @testumulo(i32 %argc) {
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; CHECK: imull
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; CHECK: testb %{{.+}}, %{{.+}}
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; CHECK: je [[NOOVERFLOWLABEL:.+]]
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; CHECK: {{.*}}[[NOOVERFLOWLABEL]]:
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; CHECK-NEXT: movb
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; CHECK-NEXT: retl
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top:
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%RHS = trunc i32 %argc to i8
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%umul = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 25, i8 %RHS)
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%ex = extractvalue { i8, i1 } %umul, 1
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br i1 %ex, label %overflow, label %nooverlow
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overflow:
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ret i8 %RHS
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nooverlow:
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%umul.value = extractvalue { i8, i1 } %umul, 0
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ret i8 %umul.value
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}
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@ -123,12 +123,9 @@ entry:
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; Check boundary conditions for large immediates.
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define zeroext i1 @saddo.i64imm2(i64 %v1, i64* %res) {
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entry:
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; SDAG-LABEL: saddo.i64imm2
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; SDAG: addq $-2147483648, %rdi
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; SDAG-NEXT: seto %al
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; FAST-LABEL: saddo.i64imm2
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; FAST: addq $-2147483648, %rdi
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; FAST-NEXT: seto %al
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; CHECK-LABEL: saddo.i64imm2
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; CHECK: addq $-2147483648, %rdi
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; CHECK-NEXT: seto %al
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%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -2147483648)
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%val = extractvalue {i64, i1} %t, 0
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%obit = extractvalue {i64, i1} %t, 1
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@ -297,10 +294,10 @@ entry:
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; SMULO
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define zeroext i1 @smulo.i8(i8 %v1, i8 %v2, i8* %res) {
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entry:
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; FAST-LABEL: smulo.i8
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; FAST: movb %dil, %al
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; FAST-NEXT: imulb %sil
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; FAST-NEXT: seto %cl
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; CHECK-LABEL: smulo.i8
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; CHECK: movb %dil, %al
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; CHECK-NEXT: imulb %sil
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; CHECK-NEXT: seto %cl
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%t = call {i8, i1} @llvm.smul.with.overflow.i8(i8 %v1, i8 %v2)
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%val = extractvalue {i8, i1} %t, 0
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%obit = extractvalue {i8, i1} %t, 1
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@ -347,10 +344,10 @@ entry:
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; UMULO
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define zeroext i1 @umulo.i8(i8 %v1, i8 %v2, i8* %res) {
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entry:
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; FAST-LABEL: umulo.i8
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; FAST: movb %dil, %al
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; FAST-NEXT: mulb %sil
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; FAST-NEXT: seto %cl
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; CHECK-LABEL: umulo.i8
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; CHECK: movb %dil, %al
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; CHECK-NEXT: mulb %sil
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; CHECK-NEXT: seto %cl
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%t = call {i8, i1} @llvm.umul.with.overflow.i8(i8 %v1, i8 %v2)
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%val = extractvalue {i8, i1} %t, 0
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%obit = extractvalue {i8, i1} %t, 1
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