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Add instruction itinerary for the PPC64 A2 core.

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This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2012-04-01 19:22:40 +00:00
parent 413b2e7539
commit 4d989ac93c
8 changed files with 615 additions and 4 deletions
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2
lib/Target/PowerPC/PPCSubtarget.cpp
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@@ -146,7 +146,7 @@ bool PPCSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
if (DarwinDirective == PPC::DIR_440)
if (DarwinDirective == PPC::DIR_440 || DarwinDirective == PPC::DIR_A2)
return false;
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;