6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-31 09:25:42 +00:00
Code Issues Projects Releases Wiki Activity

Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
2011-09-23 06:57:25 +00:00
parent aaa9fc2e37
commit 4da632e6e0
5 changed files with 23 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
utils/TableGen/X86RecognizableInstr.cpp
View File

@@ -231,10 +231,15 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
// Check for 64-bit inst which does not require REX
Is32Bit = false;
Is64Bit = false;
// FIXME: Is there some better way to check for In64BitMode?
std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
if (Predicates[i]->getName().find("32Bit") != Name.npos) {
Is32Bit = true;
break;
}
if (Predicates[i]->getName().find("64Bit") != Name.npos) {
Is64Bit = true;
break;
@@ -947,7 +952,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(),
currentOpcode,
*filter,
UID);
UID, Is32Bit);
Spec->modifierType = MODIFIER_OPCODE;
Spec->modifierBase = opcodeToSet;
@@ -957,14 +962,14 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
insnContext(),
opcodeToSet,
*filter,
UID);
UID, Is32Bit);
}
} else {
tables.setTableFields(opcodeType,
insnContext(),
opcodeToSet,
*filter,
UID);
UID, Is32Bit);
Spec->modifierType = MODIFIER_NONE;
Spec->modifierBase = opcodeToSet;