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Replace some bit operations with simpler ones. No functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-05-19 22:01:57 +00:00
parent 634123e98d
commit 4dc8bdf87d
3 changed files with 9 additions and 12 deletions
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16
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -10434,17 +10434,15 @@ ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
bool ARM::isBitFieldInvertedMask(unsigned v) {
if (v == 0xffffffff)
return 0;
return false;
// there can be 1's on either or both "outsides", all the "inside"
// bits must be 0's
unsigned int lsb = 0, msb = 31;
while (v & (1 << msb)) --msb;
while (v & (1 << lsb)) ++lsb;
for (unsigned int i = lsb; i <= msb; ++i) {
if (v & (1 << i))
return 0;
}
return 1;
unsigned TO = CountTrailingOnes_32(v);
unsigned LO = CountLeadingOnes_32(v);
v = (v >> TO) << TO;
v = (v << LO) >> LO;
return v == 0;
}
/// isFPImmLegal - Returns true if the target can instruction select the

3
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -7423,8 +7423,7 @@ processInstruction(MCInst &Inst,
unsigned TZ = CountTrailingZeros_32(Mask);
if ((Inst.getOperand(0).getImm() & 1) == 0) {
assert(Mask && TZ <= 3 && "illegal IT mask value!");
for (unsigned i = 3; i != TZ; --i)
Mask ^= 1 << i;
Mask ^= (0xE << TZ) & 0xF;
}
MO.setImm(Mask);

2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -1224,7 +1224,7 @@ static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
}
// Empty register lists are not allowed.
if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
if (Val == 0) return MCDisassembler::Fail;
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))