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Create a PPC440 SchedMachineModel

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Some of the older PPC processor definitions don't have associated
SchedMachineModels; correct this for the PPC440.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel 2013-11-29 06:32:17 +00:00
parent 6e33f489a1
commit 4dd359fcde
2 changed files with 20 additions and 6 deletions
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12
lib/Target/PowerPC/PPC.td
View File

@ -153,12 +153,12 @@ include "PPCInstrInfo.td"
//
def : Processor<"generic", G3Itineraries, [Directive32]>;
def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE,
FeatureBookE, DeprecatedMFTB]>;
def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE,
FeatureBookE, DeprecatedMFTB]>;
def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE,
FeatureBookE, DeprecatedMFTB]>;
def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
FeatureFRES, FeatureFRSQRTE,
FeatureBookE, DeprecatedMFTB]>;
def : Processor<"601", G3Itineraries, [Directive601]>;
def : Processor<"602", G3Itineraries, [Directive602]>;
def : Processor<"603", G3Itineraries, [Directive603,

14
lib/Target/PowerPC/PPCSchedule440.td
View File

@ -555,3 +555,17 @@ def PPC440Itineraries : ProcessorItineraries<
[6, 0],
[P440_FPR_Bypass, P440_FPR_Bypass]>
]>;
// ===---------------------------------------------------------------------===//
// PPC440 machine model for scheduling and other instruction cost heuristics.
def PPC440Model : SchedMachineModel {
let IssueWidth = 2; // 2 instructions are dispatched per cycle.
let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
let LoadLatency = 5; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let Itineraries = PPC440Itineraries;
}