mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Jump table JIT support. Work in progress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
47c01a0099
commit
4df60f5491
@ -28,10 +28,14 @@
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#ifndef NDEBUG
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#include <iomanip>
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#endif
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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@ -44,16 +48,20 @@ namespace {
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TargetMachine &TM;
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MachineCodeEmitter &MCE;
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const std::vector<MachineConstantPoolEntry> *MCPEs;
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const std::vector<MachineJumpTableEntry> *MJTEs;
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bool IsPIC;
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public:
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static char ID;
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explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
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: MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
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MCE(mce), MCPEs(0) {}
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MCE(mce), MCPEs(0), MJTEs(0),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
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const ARMInstrInfo &ii, const TargetData &td)
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: MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
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MCE(mce), MCPEs(0) {}
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MCE(mce), MCPEs(0), MJTEs(0),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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bool runOnMachineFunction(MachineFunction &MF);
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@ -71,6 +79,8 @@ namespace {
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void emitMOVi2piecesInstruction(const MachineInstr &MI);
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void emitLEApcrelJTInstruction(const MachineInstr &MI);
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void addPCLabel(unsigned LabelID);
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void emitPseudoInstruction(const MachineInstr &MI);
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@ -89,6 +99,7 @@ namespace {
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unsigned ImplicitRn = 0);
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void emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRd = 0,
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unsigned ImplicitRn = 0);
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void emitMiscLoadStoreInstruction(const MachineInstr &MI,
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@ -104,6 +115,8 @@ namespace {
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void emitBranchInstruction(const MachineInstr &MI);
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void emitInlineJumpTable(unsigned JTIndex, intptr_t JTBase);
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void emitMiscBranchInstruction(const MachineInstr &MI);
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/// getBinaryCodeForInstr - This function, generated by the
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@ -133,7 +146,7 @@ namespace {
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void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
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unsigned PCAdj = 0);
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void emitGlobalConstant(const Constant *CV);
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void emitMachineBasicBlock(MachineBasicBlock *BB);
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void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc);
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};
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char ARMCodeEmitter::ID = 0;
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}
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@ -153,7 +166,9 @@ bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
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JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
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MCPEs = &MF.getConstantPool()->getConstants();
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JTI->Initialize(MCPEs);
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MJTEs = &MF.getJumpTableInfo()->getJumpTables();
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IsPIC = TM.getRelocationModel() == Reloc::PIC_;
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JTI->Initialize(MF);
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do {
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DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
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@ -201,7 +216,7 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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else if (MO.isJTI())
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emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
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else if (MO.isMBB())
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emitMachineBasicBlock(MO.getMBB());
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emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
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else {
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cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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abort();
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@ -242,17 +257,21 @@ void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
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unsigned PCAdj /* = 0 */) {
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTIndex, PCAdj));
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Reloc, JTIndex, PCAdj, true));
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}
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/// emitMachineBasicBlock - Emit the specified address basic block.
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void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
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void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
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unsigned Reloc) {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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ARM::reloc_arm_branch, BB));
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Reloc, BB));
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}
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void ARMCodeEmitter::emitWordLE(unsigned Binary) {
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DOUT << " " << (void*)Binary << "\n";
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#ifndef NDEBUG
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DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0')
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<< Binary << std::dec << "\n";
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#endif
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MCE.emitWordLE(Binary);
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}
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@ -389,6 +408,34 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
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// It's basically add r, pc, (LJTI - $+8)
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const TargetInstrDesc &TID = MI.getDesc();
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// Emit the 'add' instruction.
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unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrModeSBit(MI, TID);
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// Encode Rd.
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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// Encode Rn which is PC.
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Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
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// Encode the displacement.
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// Set bit I(25) to identify this is the immediate form of <shifter_op>.
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Binary |= 1 << ARMII::I_BitShift;
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emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
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DOUT << " ** LPC" << LabelID << " @ "
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<< (void*)MCE.getCurrentPCValue() << '\n';
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@ -417,7 +464,7 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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// Remember of the address of the PC label for relocation later.
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addPCLabel(MI.getOperand(2).getImm());
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// These are just load / store instructions that implicitly read pc.
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emitLoadStoreInstruction(MI, ARM::PC);
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emitLoadStoreInstruction(MI, 0, ARM::PC);
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break;
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}
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case ARM::PICLDRH:
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@ -434,6 +481,10 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
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// Two instructions to materialize a constant.
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emitMOVi2piecesInstruction(MI);
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break;
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case ARM::LEApcrelJT:
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// Materialize jumptable address.
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emitLEApcrelJTInstruction(MI);
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break;
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}
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}
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@ -569,7 +620,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
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}
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// Encode so_imm.
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// Set bit I(25) to identify this is the immediate form of <shifter_op>
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// Set bit I(25) to identify this is the immediate form of <shifter_op>.
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Binary |= 1 << ARMII::I_BitShift;
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Binary |= getMachineSoImmOpValue(MO.getImm());
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@ -577,6 +628,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
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}
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void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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unsigned ImplicitRd,
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unsigned ImplicitRn) {
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -585,18 +637,21 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
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Binary |= II->getPredicate(&MI) << ARMII::CondShift;
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// Set first operand
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Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
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unsigned OpIdx = 0;
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if (ImplicitRd)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
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<< ARMII::RegRdShift);
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else
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
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// Set second operand
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unsigned OpIdx = 1;
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if (ImplicitRn)
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
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<< ARMII::RegRnShift);
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else {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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else
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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unsigned AM2Opc = (ImplicitRn == ARM::PC)
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@ -646,10 +701,8 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
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// Special handling for implicit use (e.g. PC).
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Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
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<< ARMII::RegRnShift);
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else {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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else
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
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const MachineOperand &MO2 = MI.getOperand(OpIdx);
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unsigned AM3Opc = (ImplicitRn == ARM::PC)
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@ -851,14 +904,40 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
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emitWordLE(Binary);
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}
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void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex, intptr_t JTBase) {
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// Remember the base address of the inline jump table.
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JTI->addJumpTableBaseAddr(JTIndex, MCE.getCurrentPCValue());
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// Now emit the jump table entries.
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const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
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for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
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if (IsPIC)
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// DestBB address - JT base.
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MCE.addRelocation(MachineRelocation::getBB(JTBase, ARM::reloc_arm_pic_jt,
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MBBs[i]));
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else
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// Absolute DestBB address.
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emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
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emitWordLE(0);
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}
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}
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void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
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const TargetInstrDesc &TID = MI.getDesc();
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if (TID.Opcode == ARM::BX ||
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TID.Opcode == ARM::BR_JTr ||
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TID.Opcode == ARM::BR_JTm ||
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TID.Opcode == ARM::BR_JTadd)
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abort(); // FIXME
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if (TID.Opcode == ARM::BR_JTm) {
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// First emit a ldr pc, [] instruction.
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emitLoadStoreInstruction(MI, ARM::PC);
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// Then emit the inline jump table.
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emitInlineJumpTable(MI.getOperand(3).getIndex(), MCE.getCurrentPCOffset());
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return;
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}
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// Part of binary is determined by TableGn.
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unsigned Binary = getBinaryCodeForInstr(MI);
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@ -151,33 +151,9 @@ class ABXIx2<dag oops, dag iops, string asm, list<dag> pattern>
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"", pattern>;
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// BR_JT instructions
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// == mov pc
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class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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class JTI<dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BrMiscFrm,
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asm, "", pattern> {
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let Inst{20} = 0; // S Bit
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let Inst{24-21} = opcod;
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let Inst{27-26} = {0,0};
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}
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// == add pc
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class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BrMiscFrm,
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asm, "", pattern> {
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let Inst{20} = 0; // S bit
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let Inst{24-21} = opcod;
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let Inst{27-26} = {0,0};
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}
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// == ldr pc
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class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
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: XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BrMiscFrm,
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asm, "", pattern> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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asm, "", pattern>;
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// addrmode1 instructions
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class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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@ -572,23 +572,35 @@ let isBranch = 1, isTerminator = 1 in {
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[(br bb:$target)]>;
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let isNotDuplicable = 1, isIndirectBranch = 1 in {
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def BR_JTr : JTI<0b1101, (outs),
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(ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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def BR_JTr : JTI<(outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
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"mov pc, $target \n$jt",
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
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def BR_JTm : JTI2<0, (outs),
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(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
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"ldr pc, $target \n$jt",
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[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
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imm:$id)]>;
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def BR_JTadd : JTI1<0b0100, (outs),
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(ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
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i32imm:$id),
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"add pc, $target, $idx \n$jt",
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[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
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imm:$id)]>;
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[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]> {
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let Inst{20} = 0; // S Bit
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let Inst{24-21} = 0b1101;
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let Inst{27-26} = {0,0};
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}
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def BR_JTm : JTI<(outs),
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(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
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"ldr pc, $target \n$jt",
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[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
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imm:$id)]> {
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let Inst{20} = 1; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = 0; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = {0,1};
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}
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def BR_JTadd : JTI<(outs),
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(ins GPR:$target, GPR:$idx, jtblock_operand:$jt, i32imm:$id),
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"add pc, $target, $idx \n$jt",
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[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
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imm:$id)]> {
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let Inst{20} = 0; // S bit
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let Inst{24-21} = 0b0100;
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let Inst{27-26} = {0,0};
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}
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} // isNotDuplicable = 1, isIndirectBranch = 1
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} // isBarrier = 1
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// FIXME: should be able to write a pattern for ARMBrcond, but can't use
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// a two-value operand where a dag node expects two operands. :(
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@ -168,9 +168,11 @@ void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
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return MCE.finishFunctionStub(F);
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}
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intptr_t ARMJITInfo::resolveRelocationAddr(MachineRelocation *MR) const {
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intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const {
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ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
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if (RT == ARM::reloc_arm_cp_entry)
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if (RT == ARM::reloc_arm_jt_base)
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return getJumpTableBaseAddr(MR->getJumpTableIndex());
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else if (RT == ARM::reloc_arm_cp_entry)
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return getConstantPoolEntryAddr(MR->getConstantPoolIndex());
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else if (RT == ARM::reloc_arm_machine_cp_entry) {
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const MachineConstantPoolEntry &MCPE = (*MCPEs)[MR->getConstantVal()];
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@ -196,7 +198,7 @@ void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
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void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
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// If this is a constpool relocation, get the address of the
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// constpool_entry instruction.
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intptr_t ResultPtr = resolveRelocationAddr(MR);
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intptr_t ResultPtr = resolveRelocDestAddr(MR);
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switch ((ARM::RelocationType)MR->getRelocationType()) {
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case ARM::reloc_arm_cp_entry:
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case ARM::reloc_arm_relative: {
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@ -221,7 +223,7 @@ void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
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case ARM::reloc_arm_machine_cp_entry:
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case ARM::reloc_arm_absolute: {
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// These addresses have already been resolved.
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*((unsigned*)RelocPos) += (unsigned)ResultPtr;
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*((unsigned*)RelocPos) |= (unsigned)ResultPtr;
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break;
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}
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case ARM::reloc_arm_branch: {
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@ -230,12 +232,24 @@ void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
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// byte offset, which must be inside the range -33554432 and +33554428.
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// Then, we set the signed_immed_24 field of the instruction to bits
|
||||
// [25:2] of the byte offset. More details ARM-ARM p. A4-11.
|
||||
ResultPtr = ResultPtr-(intptr_t)RelocPos-8;
|
||||
ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
|
||||
ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2;
|
||||
assert(ResultPtr >= -33554432 && ResultPtr <= 33554428);
|
||||
*((unsigned*)RelocPos) |= ResultPtr;
|
||||
break;
|
||||
}
|
||||
case ARM::reloc_arm_jt_base: {
|
||||
// JT base - (instruction addr + 8)
|
||||
ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
|
||||
*((unsigned*)RelocPos) |= ResultPtr;
|
||||
break;
|
||||
}
|
||||
case ARM::reloc_arm_pic_jt: {
|
||||
// PIC JT entry is destination - JT base.
|
||||
ResultPtr = ResultPtr - (intptr_t)RelocPos;
|
||||
*((unsigned*)RelocPos) |= ResultPtr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -16,6 +16,8 @@
|
||||
|
||||
#include "llvm/Target/TargetJITInfo.h"
|
||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineJumpTableInfo.h"
|
||||
#include "llvm/ADT/DenseMap.h"
|
||||
#include "llvm/ADT/SmallVector.h"
|
||||
|
||||
@ -31,7 +33,11 @@ namespace llvm {
|
||||
|
||||
// ConstPoolId2AddrMap - A map from constant pool ids to the corresponding
|
||||
// CONSTPOOL_ENTRY addresses.
|
||||
SmallVector<intptr_t, 32> ConstPoolId2AddrMap;
|
||||
SmallVector<intptr_t, 16> ConstPoolId2AddrMap;
|
||||
|
||||
// JumpTableId2AddrMap - A map from inline jumptable ids to the
|
||||
// corresponding inline jump table bases.
|
||||
SmallVector<intptr_t, 16> JumpTableId2AddrMap;
|
||||
|
||||
// PCLabelMap - A map from PC labels to addresses.
|
||||
DenseMap<unsigned, intptr_t> PCLabelMap;
|
||||
@ -65,6 +71,10 @@ namespace llvm {
|
||||
/// pool address resolution is handled by the target.
|
||||
virtual bool hasCustomConstantPool() const { return true; }
|
||||
|
||||
/// hasCustomJumpTables - Allows a target to specify that jumptables
|
||||
/// are emitted by the target.
|
||||
virtual bool hasCustomJumpTables() const { return true; }
|
||||
|
||||
/// allocateSeparateGVMemory - If true, globals should be placed in
|
||||
/// separately allocated heap memory rather than in the same
|
||||
/// code memory allocated by MachineCodeEmitter.
|
||||
@ -78,20 +88,21 @@ namespace llvm {
|
||||
|
||||
/// Initialize - Initialize internal stage. Get the list of constant pool
|
||||
/// Resize constant pool ids to CONSTPOOL_ENTRY addresses map.
|
||||
void Initialize(const std::vector<MachineConstantPoolEntry> *mcpes) {
|
||||
MCPEs = mcpes;
|
||||
void Initialize(const MachineFunction &MF) {
|
||||
MCPEs = &MF.getConstantPool()->getConstants();
|
||||
ConstPoolId2AddrMap.resize(MCPEs->size());
|
||||
JumpTableId2AddrMap.resize(MF.getJumpTableInfo()->getJumpTables().size());
|
||||
}
|
||||
|
||||
/// getConstantPoolEntryAddr - The ARM target puts all constant
|
||||
/// pool entries into constant islands. Resolve the constant pool index
|
||||
/// into the address where the constant is stored.
|
||||
/// pool entries into constant islands. This returns the address of the
|
||||
/// constant pool entry of the specified index.
|
||||
intptr_t getConstantPoolEntryAddr(unsigned CPI) const {
|
||||
assert(CPI < ConstPoolId2AddrMap.size());
|
||||
return ConstPoolId2AddrMap[CPI];
|
||||
}
|
||||
|
||||
/// addConstantPoolEntryAddr - Map a Constant Pool Index (CPI) to the address
|
||||
/// addConstantPoolEntryAddr - Map a Constant Pool Index to the address
|
||||
/// where its associated value is stored. When relocations are processed,
|
||||
/// this value will be used to resolve references to the constant.
|
||||
void addConstantPoolEntryAddr(unsigned CPI, intptr_t Addr) {
|
||||
@ -99,6 +110,23 @@ namespace llvm {
|
||||
ConstPoolId2AddrMap[CPI] = Addr;
|
||||
}
|
||||
|
||||
/// getJumpTableBaseAddr - The ARM target inline all jump tables within
|
||||
/// text section of the function. This returns the address of the base of
|
||||
/// the jump table of the specified index.
|
||||
intptr_t getJumpTableBaseAddr(unsigned JTI) const {
|
||||
assert(JTI < JumpTableId2AddrMap.size());
|
||||
return JumpTableId2AddrMap[JTI];
|
||||
}
|
||||
|
||||
/// addJumpTableBaseAddr - Map a jump table index to the address where
|
||||
/// the corresponding inline jump table is emitted. When relocations are
|
||||
/// processed, this value will be used to resolve references to the
|
||||
/// jump table.
|
||||
void addJumpTableBaseAddr(unsigned JTI, intptr_t Addr) {
|
||||
assert(JTI < JumpTableId2AddrMap.size());
|
||||
JumpTableId2AddrMap[JTI] = Addr;
|
||||
}
|
||||
|
||||
/// getPCLabelAddr - Retrieve the address of the PC label of the specified id.
|
||||
intptr_t getPCLabelAddr(unsigned Id) const {
|
||||
DenseMap<unsigned, intptr_t>::const_iterator I = PCLabelMap.find(Id);
|
||||
@ -112,10 +140,10 @@ namespace llvm {
|
||||
}
|
||||
|
||||
private:
|
||||
/// resolveRelocationAddr - Resolve the resulting address of the relocation
|
||||
/// resolveRelocDestAddr - Resolve the resulting address of the relocation
|
||||
/// if it's not already solved. Constantpool entries must be resolved by
|
||||
/// ARM target.
|
||||
intptr_t resolveRelocationAddr(MachineRelocation *MR) const;
|
||||
intptr_t resolveRelocDestAddr(MachineRelocation *MR) const;
|
||||
};
|
||||
}
|
||||
|
||||
|
||||
@ -35,6 +35,13 @@ namespace llvm {
|
||||
// entry.
|
||||
reloc_arm_machine_cp_entry,
|
||||
|
||||
// reloc_arm_jt_base - PC relative relocation for jump tables whose
|
||||
// addresses are kept locally in a map.
|
||||
reloc_arm_jt_base,
|
||||
|
||||
// reloc_arm_pic_jt - PIC jump table entry relocation: dest bb - jt base.
|
||||
reloc_arm_pic_jt,
|
||||
|
||||
// reloc_arm_branch - Branch address relocation.
|
||||
reloc_arm_branch
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user