mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 04:30:23 +00:00
[mips] Move MipsTargetLowering::lowerINTRINSIC_W_CHAIN and
lowerINTRINSIC_WO_CHAIN into MipsSETargetLowering. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179444 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
69893a224d
commit
4e0980af2e
@ -30,7 +30,6 @@
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/GlobalVariable.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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@ -346,9 +345,6 @@ MipsTargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
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// Use the default for now
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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@ -746,8 +742,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
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case ISD::LOAD: return lowerLOAD(Op, DAG);
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case ISD::STORE: return lowerSTORE(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
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case ISD::ADD: return lowerADD(Op, DAG);
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}
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return SDValue();
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@ -2050,170 +2044,6 @@ SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
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}
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static SDValue initAccumulator(SDValue In, DebugLoc DL, SelectionDAG &DAG) {
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SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
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DAG.getConstant(0, MVT::i32));
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SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
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DAG.getConstant(1, MVT::i32));
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return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
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}
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static SDValue extractLOHI(SDValue Op, DebugLoc DL, SelectionDAG &DAG) {
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SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
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DAG.getConstant(Mips::sub_lo, MVT::i32));
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SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
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DAG.getConstant(Mips::sub_hi, MVT::i32));
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return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
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}
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// This function expands mips intrinsic nodes which have 64-bit input operands
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// or output values.
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//
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// out64 = intrinsic-node in64
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// =>
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// lo = copy (extract-element (in64, 0))
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// hi = copy (extract-element (in64, 1))
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// mips-specific-node
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// v0 = copy lo
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// v1 = copy hi
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// out64 = merge-values (v0, v1)
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//
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static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
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DebugLoc DL = Op.getDebugLoc();
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bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
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SmallVector<SDValue, 3> Ops;
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unsigned OpNo = 0;
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// See if Op has a chain input.
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if (HasChainIn)
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Ops.push_back(Op->getOperand(OpNo++));
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// The next operand is the intrinsic opcode.
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assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
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// See if the next operand has type i64.
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SDValue Opnd = Op->getOperand(++OpNo), In64;
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if (Opnd.getValueType() == MVT::i64)
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In64 = initAccumulator(Opnd, DL, DAG);
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else
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Ops.push_back(Opnd);
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// Push the remaining operands.
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for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
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Ops.push_back(Op->getOperand(OpNo));
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// Add In64 to the end of the list.
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if (In64.getNode())
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Ops.push_back(In64);
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// Scan output.
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SmallVector<EVT, 2> ResTys;
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for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
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I != E; ++I)
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ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
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// Create node.
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SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
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SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
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if (!HasChainIn)
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return Out;
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assert(Val->getValueType(1) == MVT::Other);
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SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
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return DAG.getMergeValues(Vals, 2, DL);
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}
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SDValue MipsTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
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default:
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return SDValue();
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case Intrinsic::mips_shilo:
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return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
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case Intrinsic::mips_dpau_h_qbl:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
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case Intrinsic::mips_dpau_h_qbr:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
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case Intrinsic::mips_dpsu_h_qbl:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
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case Intrinsic::mips_dpsu_h_qbr:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
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case Intrinsic::mips_dpa_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
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case Intrinsic::mips_dps_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
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case Intrinsic::mips_dpax_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
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case Intrinsic::mips_dpsx_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
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case Intrinsic::mips_mulsa_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
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case Intrinsic::mips_mult:
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return lowerDSPIntr(Op, DAG, MipsISD::Mult);
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case Intrinsic::mips_multu:
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return lowerDSPIntr(Op, DAG, MipsISD::Multu);
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case Intrinsic::mips_madd:
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return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
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case Intrinsic::mips_maddu:
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return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
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case Intrinsic::mips_msub:
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return lowerDSPIntr(Op, DAG, MipsISD::MSub);
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case Intrinsic::mips_msubu:
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return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
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}
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}
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SDValue MipsTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
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default:
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return SDValue();
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case Intrinsic::mips_extp:
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return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
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case Intrinsic::mips_extpdp:
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return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
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case Intrinsic::mips_extr_w:
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return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
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case Intrinsic::mips_extr_r_w:
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return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
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case Intrinsic::mips_extr_rs_w:
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return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
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case Intrinsic::mips_extr_s_h:
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return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
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case Intrinsic::mips_mthlip:
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return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
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case Intrinsic::mips_mulsaq_s_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
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case Intrinsic::mips_maq_s_w_phl:
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return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
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case Intrinsic::mips_maq_s_w_phr:
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return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
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case Intrinsic::mips_maq_sa_w_phl:
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return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
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case Intrinsic::mips_maq_sa_w_phr:
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return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
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case Intrinsic::mips_dpaq_s_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
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case Intrinsic::mips_dpsq_s_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
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case Intrinsic::mips_dpaq_sa_l_w:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
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case Intrinsic::mips_dpsq_sa_l_w:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
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case Intrinsic::mips_dpaqx_s_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
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case Intrinsic::mips_dpaqx_sa_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
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case Intrinsic::mips_dpsqx_s_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
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case Intrinsic::mips_dpsqx_sa_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
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}
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}
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SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
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if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
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|| cast<ConstantSDNode>
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@ -345,8 +345,6 @@ namespace llvm {
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bool IsSRA) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
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/// isEligibleForTailCallOptimization - Check whether the call is eligible
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@ -15,6 +15,7 @@
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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@ -79,6 +80,9 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM)
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setOperationAction(ISD::MUL, MVT::i64, Custom);
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}
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
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setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
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@ -125,6 +129,8 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
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case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
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case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
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case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
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}
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return MipsTargetLowering::LowerOperation(Op, DAG);
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@ -389,6 +395,171 @@ SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
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return DAG.getMergeValues(Vals, 2, DL);
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}
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static SDValue initAccumulator(SDValue In, DebugLoc DL, SelectionDAG &DAG) {
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SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
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DAG.getConstant(0, MVT::i32));
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SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
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DAG.getConstant(1, MVT::i32));
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return DAG.getNode(MipsISD::InsertLOHI, DL, MVT::Untyped, InLo, InHi);
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}
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static SDValue extractLOHI(SDValue Op, DebugLoc DL, SelectionDAG &DAG) {
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SDValue Lo = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
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DAG.getConstant(Mips::sub_lo, MVT::i32));
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SDValue Hi = DAG.getNode(MipsISD::ExtractLOHI, DL, MVT::i32, Op,
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DAG.getConstant(Mips::sub_hi, MVT::i32));
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return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
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}
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// This function expands mips intrinsic nodes which have 64-bit input operands
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// or output values.
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//
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// out64 = intrinsic-node in64
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// =>
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// lo = copy (extract-element (in64, 0))
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// hi = copy (extract-element (in64, 1))
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// mips-specific-node
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// v0 = copy lo
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// v1 = copy hi
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// out64 = merge-values (v0, v1)
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//
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static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
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DebugLoc DL = Op.getDebugLoc();
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bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
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SmallVector<SDValue, 3> Ops;
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unsigned OpNo = 0;
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// See if Op has a chain input.
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if (HasChainIn)
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Ops.push_back(Op->getOperand(OpNo++));
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// The next operand is the intrinsic opcode.
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assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
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// See if the next operand has type i64.
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SDValue Opnd = Op->getOperand(++OpNo), In64;
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if (Opnd.getValueType() == MVT::i64)
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In64 = initAccumulator(Opnd, DL, DAG);
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else
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Ops.push_back(Opnd);
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// Push the remaining operands.
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for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
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Ops.push_back(Op->getOperand(OpNo));
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// Add In64 to the end of the list.
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if (In64.getNode())
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Ops.push_back(In64);
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// Scan output.
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SmallVector<EVT, 2> ResTys;
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for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
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I != E; ++I)
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ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
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// Create node.
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SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size());
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SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
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if (!HasChainIn)
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return Out;
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assert(Val->getValueType(1) == MVT::Other);
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SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
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return DAG.getMergeValues(Vals, 2, DL);
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}
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SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
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default:
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return SDValue();
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case Intrinsic::mips_shilo:
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return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
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case Intrinsic::mips_dpau_h_qbl:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
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case Intrinsic::mips_dpau_h_qbr:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
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case Intrinsic::mips_dpsu_h_qbl:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
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case Intrinsic::mips_dpsu_h_qbr:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
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case Intrinsic::mips_dpa_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
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case Intrinsic::mips_dps_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
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case Intrinsic::mips_dpax_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
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case Intrinsic::mips_dpsx_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
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case Intrinsic::mips_mulsa_w_ph:
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return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
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case Intrinsic::mips_mult:
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return lowerDSPIntr(Op, DAG, MipsISD::Mult);
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case Intrinsic::mips_multu:
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return lowerDSPIntr(Op, DAG, MipsISD::Multu);
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case Intrinsic::mips_madd:
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return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
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case Intrinsic::mips_maddu:
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return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
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case Intrinsic::mips_msub:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MSub);
|
||||
case Intrinsic::mips_msubu:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
|
||||
}
|
||||
}
|
||||
|
||||
SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
switch (cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue()) {
|
||||
default:
|
||||
return SDValue();
|
||||
case Intrinsic::mips_extp:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
|
||||
case Intrinsic::mips_extpdp:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
|
||||
case Intrinsic::mips_extr_w:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
|
||||
case Intrinsic::mips_extr_r_w:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
|
||||
case Intrinsic::mips_extr_rs_w:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
|
||||
case Intrinsic::mips_extr_s_h:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
|
||||
case Intrinsic::mips_mthlip:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
|
||||
case Intrinsic::mips_mulsaq_s_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
|
||||
case Intrinsic::mips_maq_s_w_phl:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
|
||||
case Intrinsic::mips_maq_s_w_phr:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
|
||||
case Intrinsic::mips_maq_sa_w_phl:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
|
||||
case Intrinsic::mips_maq_sa_w_phr:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
|
||||
case Intrinsic::mips_dpaq_s_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
|
||||
case Intrinsic::mips_dpsq_s_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
|
||||
case Intrinsic::mips_dpaq_sa_l_w:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
|
||||
case Intrinsic::mips_dpsq_sa_l_w:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
|
||||
case Intrinsic::mips_dpaqx_s_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
|
||||
case Intrinsic::mips_dpaqx_sa_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
|
||||
case Intrinsic::mips_dpsqx_s_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
|
||||
case Intrinsic::mips_dpsqx_sa_w_ph:
|
||||
return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
|
||||
}
|
||||
}
|
||||
|
||||
MachineBasicBlock * MipsSETargetLowering::
|
||||
emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
|
||||
// $bb:
|
||||
|
||||
@ -59,6 +59,9 @@ namespace llvm {
|
||||
SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi,
|
||||
SelectionDAG &DAG) const;
|
||||
|
||||
SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
MachineBasicBlock *emitBPOSGE32(MachineInstr *MI,
|
||||
MachineBasicBlock *BB) const;
|
||||
};
|
||||
|
||||
Loading…
Reference in New Issue
Block a user