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Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186869 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1979,22 +1979,22 @@ def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>;
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def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>;
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// div and idiv aliases for explicit A register.
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def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>;
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def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>;
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def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>;
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def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>;
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def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>;
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def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>;
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def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>;
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def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>;
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def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>;
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def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>;
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def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>;
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def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>;
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def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>;
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def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>;
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def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>;
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def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>;
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def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8r GR8 :$src)>;
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def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16r GR16:$src)>;
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def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32r GR32:$src)>;
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def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64r GR64:$src)>;
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def : InstAlias<"div{b}\t{$src, %al|AL, $src}", (DIV8m i8mem :$src)>;
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def : InstAlias<"div{w}\t{$src, %ax|AX, $src}", (DIV16m i16mem:$src)>;
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def : InstAlias<"div{l}\t{$src, %eax|EAX, $src}", (DIV32m i32mem:$src)>;
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def : InstAlias<"div{q}\t{$src, %rax|RAX, $src}", (DIV64m i64mem:$src)>;
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def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8r GR8 :$src)>;
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def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16r GR16:$src)>;
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def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32r GR32:$src)>;
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def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64r GR64:$src)>;
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def : InstAlias<"idiv{b}\t{$src, %al|AL, $src}", (IDIV8m i8mem :$src)>;
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def : InstAlias<"idiv{w}\t{$src, %ax|AX, $src}", (IDIV16m i16mem:$src)>;
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def : InstAlias<"idiv{l}\t{$src, %eax|EAX, $src}", (IDIV32m i32mem:$src)>;
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def : InstAlias<"idiv{q}\t{$src, %rax|RAX, $src}", (IDIV64m i64mem:$src)>;
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@ -2076,12 +2076,12 @@ def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>;
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def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>;
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// inb %dx -> inb %al, %dx
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def : InstAlias<"inb %dx", (IN8rr)>;
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def : InstAlias<"inw %dx", (IN16rr)>;
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def : InstAlias<"inl %dx", (IN32rr)>;
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def : InstAlias<"inb $port", (IN8ri i8imm:$port)>;
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def : InstAlias<"inw $port", (IN16ri i8imm:$port)>;
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def : InstAlias<"inl $port", (IN32ri i8imm:$port)>;
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def : InstAlias<"inb\t{%dx|DX}", (IN8rr), 0>;
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def : InstAlias<"inw\t{%dx|DX}", (IN16rr), 0>;
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def : InstAlias<"inl\t{%dx|DX}", (IN32rr), 0>;
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def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>;
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def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>;
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def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>;
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// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp
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@ -2130,12 +2130,12 @@ def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>;
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// Note: No GR32->GR64 movzx form.
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// outb %dx -> outb %al, %dx
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def : InstAlias<"outb %dx", (OUT8rr)>;
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def : InstAlias<"outw %dx", (OUT16rr)>;
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def : InstAlias<"outl %dx", (OUT32rr)>;
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def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>;
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def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>;
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def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>;
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def : InstAlias<"outb\t{%dx|DX}", (OUT8rr), 0>;
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def : InstAlias<"outw\t{%dx|DX}", (OUT16rr), 0>;
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def : InstAlias<"outl\t{%dx|DX}", (OUT32rr), 0>;
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def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>;
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def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>;
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def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>;
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// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same
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// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity
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@ -241,10 +241,10 @@ cmovnzq %rbx, %rax
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// rdar://8407928
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// CHECK: inb $127, %al
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// CHECK: inw %dx
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// CHECK: inw %dx, %ax
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// CHECK: outb %al, $127
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// CHECK: outw %dx
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// CHECK: inl %dx
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// CHECK: outw %ax, %dx
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// CHECK: inl %dx, %eax
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inb $0x7f
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inw %dx
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outb $0x7f
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@ -253,12 +253,12 @@ inl %dx
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// PR8114
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// CHECK: outb %dx
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// CHECK: outb %dx
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// CHECK: outw %dx
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// CHECK: outw %dx
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// CHECK: outl %dx
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// CHECK: outl %dx
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// CHECK: outb %al, %dx
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// CHECK: outb %al, %dx
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// CHECK: outw %ax, %dx
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// CHECK: outw %ax, %dx
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// CHECK: outl %eax, %dx
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// CHECK: outl %eax, %dx
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out %al, (%dx)
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outb %al, (%dx)
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@ -267,12 +267,12 @@ outw %ax, (%dx)
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out %eax, (%dx)
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outl %eax, (%dx)
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// CHECK: inb %dx
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// CHECK: inb %dx
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// CHECK: inw %dx
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// CHECK: inw %dx
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// CHECK: inl %dx
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// CHECK: inl %dx
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// CHECK: inb %dx, %al
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// CHECK: inb %dx, %al
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// CHECK: inw %dx, %ax
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// CHECK: inw %dx, %ax
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// CHECK: inl %dx, %eax
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// CHECK: inl %dx, %eax
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in (%dx), %al
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inb (%dx), %al
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