From 4e68c7cca44d33771d376f1668d687ce9d8f11d3 Mon Sep 17 00:00:00 2001
From: Eric Christopher <echristo@apple.com>
Date: Wed, 1 Sep 2010 18:01:32 +0000
Subject: [PATCH] Add some more load types in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112721 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMFastISel.cpp | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index 198a965c75a..87af77b13e1 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -110,6 +110,7 @@ class ARMFastISel : public FastISel {
     // Utility routines.
   private:
     bool isTypeLegal(const Type *Ty, EVT &VT);
+    bool isLoadTypeLegal(const Type *Ty, EVT &VT);
     bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
     bool ARMLoadAlloca(const Instruction *I);
     bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
@@ -317,12 +318,23 @@ bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
   
   // Only handle simple types.
   if (VT == MVT::Other || !VT.isSimple()) return false;
-  
+    
   // Handle all legal types, i.e. a register that will directly hold this
   // value.
   return TLI.isTypeLegal(VT);
 }
 
+bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
+  if (isTypeLegal(Ty, VT)) return true;
+  
+  // If this is a type than can be sign or zero-extended to a basic operation
+  // go ahead and accept it now.
+  if (VT == MVT::i8 || VT == MVT::i16)
+    return true;
+  
+  return false;
+}
+
 // Computes the Reg+Offset to get to an object.
 bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
                                       int &Offset) {
@@ -403,6 +415,14 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
     default: 
       assert(false && "Trying to emit for an unhandled type!");
       return false;
+    case MVT::i16:
+      Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
+      VT = MVT::i32;
+      break;
+    case MVT::i8:
+      Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
+      VT = MVT::i32;
+      break;
     case MVT::i32:
       Opc = isThumb ? ARM::tLDR : ARM::LDR;
       break;
@@ -432,7 +452,7 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
     
   // Verify we have a legal type before going any further.
   EVT VT;
-  if (!isTypeLegal(I->getType(), VT))
+  if (!isLoadTypeLegal(I->getType(), VT))
     return false;
   
   // Our register and offset with innocuous defaults.