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ARM/NEON: Pattern match vector integer abs to vabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180604 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4907,6 +4907,29 @@ def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
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"vabs", "f32",
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v4f32, v4f32, fabs>;
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def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
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(v2i32 (bitconvert (v8i8 (add DPR:$src,
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(NEONvshrs DPR:$src, (i32 7))))))),
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(VABSv8i8 DPR:$src)>;
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def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
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(v2i32 (bitconvert (v4i16 (add DPR:$src,
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(NEONvshrs DPR:$src, (i32 15))))))),
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(VABSv4i16 DPR:$src)>;
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def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
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(v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
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(VABSv2i32 DPR:$src)>;
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def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
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(v4i32 (bitconvert (v16i8 (add QPR:$src,
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(NEONvshrs QPR:$src, (i32 7))))))),
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(VABSv16i8 QPR:$src)>;
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def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
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(v4i32 (bitconvert (v8i16 (add QPR:$src,
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(NEONvshrs QPR:$src, (i32 15))))))),
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(VABSv8i16 QPR:$src)>;
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def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
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(v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
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(VABSv4i32 QPR:$src)>;
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def : Pat<(v2f32 (int_arm_neon_vabs (v2f32 DPR:$src))), (VABSfd DPR:$src)>;
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def : Pat<(v4f32 (int_arm_neon_vabs (v4f32 QPR:$src))), (VABSfq QPR:$src)>;
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91
test/CodeGen/ARM/neon_vabs.ll
Normal file
91
test/CodeGen/ARM/neon_vabs.ll
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@ -0,0 +1,91 @@
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; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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define <4 x i32> @test1(<4 x i32> %a) nounwind {
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; CHECK: test1:
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; CHECK: vabs.s32 q
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
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%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
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ret <4 x i32> %abs
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}
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define <4 x i32> @test2(<4 x i32> %a) nounwind {
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; CHECK: test2:
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; CHECK: vabs.s32 q
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sge <4 x i32> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
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ret <4 x i32> %abs
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}
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define <8 x i16> @test3(<8 x i16> %a) nounwind {
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; CHECK: test3:
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; CHECK: vabs.s16 q
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%tmp1neg = sub <8 x i16> zeroinitializer, %a
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%b = icmp sgt <8 x i16> %a, zeroinitializer
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%abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
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ret <8 x i16> %abs
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}
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define <16 x i8> @test4(<16 x i8> %a) nounwind {
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; CHECK: test4:
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; CHECK: vabs.s8 q
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%tmp1neg = sub <16 x i8> zeroinitializer, %a
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%b = icmp slt <16 x i8> %a, zeroinitializer
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%abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
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ret <16 x i8> %abs
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}
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define <4 x i32> @test5(<4 x i32> %a) nounwind {
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; CHECK: test5:
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; CHECK: vabs.s32 q
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%tmp1neg = sub <4 x i32> zeroinitializer, %a
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%b = icmp sle <4 x i32> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a
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ret <4 x i32> %abs
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}
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define <2 x i32> @test6(<2 x i32> %a) nounwind {
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; CHECK: test6:
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; CHECK: vabs.s32 d
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%tmp1neg = sub <2 x i32> zeroinitializer, %a
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%b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
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%abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
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ret <2 x i32> %abs
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}
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define <2 x i32> @test7(<2 x i32> %a) nounwind {
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; CHECK: test7:
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; CHECK: vabs.s32 d
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%tmp1neg = sub <2 x i32> zeroinitializer, %a
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%b = icmp sge <2 x i32> %a, zeroinitializer
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%abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
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ret <2 x i32> %abs
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}
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define <4 x i16> @test8(<4 x i16> %a) nounwind {
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; CHECK: test8:
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; CHECK: vabs.s16 d
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%tmp1neg = sub <4 x i16> zeroinitializer, %a
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%b = icmp sgt <4 x i16> %a, zeroinitializer
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%abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
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ret <4 x i16> %abs
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}
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define <8 x i8> @test9(<8 x i8> %a) nounwind {
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; CHECK: test9:
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; CHECK: vabs.s8 d
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%tmp1neg = sub <8 x i8> zeroinitializer, %a
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%b = icmp slt <8 x i8> %a, zeroinitializer
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%abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
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ret <8 x i8> %abs
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}
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define <2 x i32> @test10(<2 x i32> %a) nounwind {
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; CHECK: test10:
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; CHECK: vabs.s32 d
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%tmp1neg = sub <2 x i32> zeroinitializer, %a
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%b = icmp sle <2 x i32> %a, zeroinitializer
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%abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a
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ret <2 x i32> %abs
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}
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