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Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} instructions.

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This adds a new decoder table/namespace 'VFPV8', as these instructions have their
top 4 bits as 0b1111, while other Thumb instructions have 0b1110.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joey Gouly
2013-07-04 14:57:20 +00:00
parent 3c99602ca8
commit 4ea250524f
6 changed files with 137 additions and 2 deletions
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15
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -455,6 +455,13 @@ DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
return result;
}
MI.clear();
result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
return result;
}
MI.clear();
result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
this, STI);
@ -764,6 +771,14 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
}
}
MI.clear();
result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
UpdateThumbVFPPredicate(MI);
return result;
}
if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
MI.clear();
result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,