mirror of
https://github.com/c64scene-ar/llvm-6502.git
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X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108076 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
b0a258be2f
commit
4ea8771535
@ -1891,171 +1891,6 @@ static bool isHReg(unsigned Reg) {
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return X86::GR8_ABCD_HRegClass.contains(Reg);
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}
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bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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// Moving from ST(0) turns into FpGET_ST0_32 etc.
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if (SrcReg == X86::ST0 || SrcReg == X86::ST1) {
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// Copying from ST(0)/ST(1).
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bool isST0 = SrcReg == X86::ST0;
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unsigned Opc;
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if (DestRC == &X86::RFP32RegClass)
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Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
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else if (DestRC == &X86::RFP64RegClass)
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Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
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else {
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if (DestRC != &X86::RFP80RegClass)
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return false;
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Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
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}
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BuildMI(MBB, MI, DL, get(Opc), DestReg);
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return true;
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}
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// Moving to ST(0) turns into FpSET_ST0_32 etc.
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if (DestReg == X86::ST0 || DestReg == X86::ST1) {
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// Copying to ST(0) / ST(1).
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bool isST0 = DestReg == X86::ST0;
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unsigned Opc;
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if (SrcRC == &X86::RFP32RegClass)
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Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
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else if (SrcRC == &X86::RFP64RegClass)
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Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
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else {
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if (SrcRC != &X86::RFP80RegClass)
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return false;
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Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
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}
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BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
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return true;
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}
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// Determine if DstRC and SrcRC have a common superclass in common.
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const TargetRegisterClass *CommonRC = DestRC;
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if (DestRC == SrcRC)
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/* Source and destination have the same register class. */;
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else if (CommonRC->hasSuperClass(SrcRC))
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CommonRC = SrcRC;
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else if (!DestRC->hasSubClass(SrcRC)) {
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// Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
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// but we want to copy them as GR64. Similarly, for GR32_NOREX and
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// GR32_NOSP, copy as GR32.
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if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
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DestRC->hasSuperClass(&X86::GR64RegClass))
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CommonRC = &X86::GR64RegClass;
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else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
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DestRC->hasSuperClass(&X86::GR32RegClass))
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CommonRC = &X86::GR32RegClass;
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else if (SrcRC->hasSuperClass(&X86::GR8RegClass) &&
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DestRC->hasSuperClass(&X86::GR8RegClass))
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CommonRC = &X86::GR8RegClass;
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else
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CommonRC = 0;
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}
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if (CommonRC) {
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unsigned Opc;
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if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
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Opc = X86::MOV64rr;
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} else if (CommonRC == &X86::GR32RegClass ||
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CommonRC == &X86::GR32_NOSPRegClass) {
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Opc = X86::MOV32rr;
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} else if (CommonRC == &X86::GR16RegClass) {
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Opc = X86::MOV16rr;
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} else if (CommonRC == &X86::GR8RegClass) {
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// Copying to or from a physical H register on x86-64 requires a NOREX
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// move. Otherwise use a normal move.
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if ((isHReg(DestReg) || isHReg(SrcReg) ||
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SrcRC == &X86::GR8_ABCD_HRegClass ||
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DestRC == &X86::GR8_ABCD_HRegClass) &&
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TM.getSubtarget<X86Subtarget>().is64Bit())
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Opc = X86::MOV8rr_NOREX;
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else
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Opc = X86::MOV8rr;
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} else if (CommonRC == &X86::GR64_ABCDRegClass) {
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Opc = X86::MOV64rr;
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} else if (CommonRC == &X86::GR32_ABCDRegClass) {
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Opc = X86::MOV32rr;
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} else if (CommonRC == &X86::GR16_ABCDRegClass) {
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Opc = X86::MOV16rr;
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} else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
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Opc = X86::MOV8rr;
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} else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
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if (TM.getSubtarget<X86Subtarget>().is64Bit())
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Opc = X86::MOV8rr_NOREX;
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else
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Opc = X86::MOV8rr;
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} else if (CommonRC == &X86::GR64_NOREXRegClass ||
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CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
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Opc = X86::MOV64rr;
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} else if (CommonRC == &X86::GR32_NOREXRegClass) {
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Opc = X86::MOV32rr;
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} else if (CommonRC == &X86::GR16_NOREXRegClass) {
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Opc = X86::MOV16rr;
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} else if (CommonRC == &X86::GR8_NOREXRegClass) {
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Opc = X86::MOV8rr;
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} else if (CommonRC == &X86::GR64_TCRegClass) {
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Opc = X86::MOV64rr_TC;
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} else if (CommonRC == &X86::GR32_TCRegClass) {
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Opc = X86::MOV32rr_TC;
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} else if (CommonRC == &X86::RFP32RegClass) {
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Opc = X86::MOV_Fp3232;
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} else if (CommonRC == &X86::RFP64RegClass) {
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Opc = X86::MOV_Fp6464;
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} else if (CommonRC == &X86::RFP80RegClass) {
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Opc = X86::MOV_Fp8080;
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} else if (CommonRC == &X86::FR32RegClass) {
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Opc = X86::FsMOVAPSrr;
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} else if (CommonRC == &X86::FR64RegClass) {
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Opc = X86::FsMOVAPDrr;
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} else if (CommonRC == &X86::VR128RegClass) {
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Opc = X86::MOVAPSrr;
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} else if (CommonRC == &X86::VR64RegClass) {
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Opc = X86::MMX_MOVQ64rr;
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} else {
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return false;
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}
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BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
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return true;
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}
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// Moving EFLAGS to / from another register requires a push and a pop.
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if (SrcRC == &X86::CCRRegClass) {
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if (SrcReg != X86::EFLAGS)
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return false;
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if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
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BuildMI(MBB, MI, DL, get(X86::PUSHF64));
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BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
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return true;
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} else if (DestRC == &X86::GR32RegClass ||
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DestRC == &X86::GR32_NOSPRegClass) {
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BuildMI(MBB, MI, DL, get(X86::PUSHF32));
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BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
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return true;
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}
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} else if (DestRC == &X86::CCRRegClass) {
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if (DestReg != X86::EFLAGS)
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return false;
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if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
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BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
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BuildMI(MBB, MI, DL, get(X86::POPF64));
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return true;
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} else if (SrcRC == &X86::GR32RegClass ||
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DestRC == &X86::GR32_NOSPRegClass) {
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BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
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BuildMI(MBB, MI, DL, get(X86::POPF32));
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return true;
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}
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}
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// Not yet supported!
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return false;
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}
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void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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@ -692,12 +692,6 @@ public:
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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