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https://github.com/c64scene-ar/llvm-6502.git
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Conditional branches and comparisons
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
c7b71bede4
commit
4ec3e5ffd1
@ -22,12 +22,26 @@ namespace llvm {
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class FunctionPass;
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class raw_ostream;
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namespace SystemZCC {
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// SystemZ specific condition code. These correspond to SYSTEMZ_*_COND in
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// SystemZInstrInfo.td. They must be kept in synch.
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enum CondCodes {
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E = 0,
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NE = 1,
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H = 2,
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L = 3,
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HE = 4,
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LE = 5
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};
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}
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FunctionPass *createSystemZISelDag(SystemZTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createSystemZCodePrinterPass(raw_ostream &o,
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SystemZTargetMachine &tm,
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CodeGenOpt::Level OptLevel,
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bool verbose);
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} // end namespace llvm;
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// Defines symbolic names for SystemZ registers.
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@ -57,6 +57,10 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setSchedulingPreference(SchedulingForLatency);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::i32, Custom);
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setOperationAction(ISD::BR_CC, MVT::i64, Custom);
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}
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SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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@ -64,6 +68,7 @@ SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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default:
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assert(0 && "unimplemented operand");
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return SDValue();
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@ -406,10 +411,75 @@ SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
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}
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SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
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ISD::CondCode CC, SDValue &SystemZCC,
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SelectionDAG &DAG) {
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assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
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// FIXME: Emit a test if RHS is zero
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bool isUnsigned = false;
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SystemZCC::CondCodes TCC;
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switch (CC) {
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default: assert(0 && "Invalid integer condition!");
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case ISD::SETEQ:
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TCC = SystemZCC::E;
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break;
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case ISD::SETNE:
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TCC = SystemZCC::NE;
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break;
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case ISD::SETULE:
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isUnsigned = true; // FALLTHROUGH
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case ISD::SETLE:
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TCC = SystemZCC::LE;
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break;
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case ISD::SETUGE:
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isUnsigned = true; // FALLTHROUGH
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case ISD::SETGE:
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TCC = SystemZCC::HE;
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break;
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case ISD::SETUGT:
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isUnsigned = true;
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case ISD::SETGT:
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TCC = SystemZCC::H; // FALLTHROUGH
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break;
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case ISD::SETULT:
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isUnsigned = true;
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case ISD::SETLT: // FALLTHROUGH
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TCC = SystemZCC::L;
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break;
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}
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SystemZCC = DAG.getConstant(TCC, MVT::i32);
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DebugLoc dl = LHS.getDebugLoc();
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return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
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dl, MVT::Flag, LHS, RHS);
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}
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SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
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SDValue Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDValue LHS = Op.getOperand(2);
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SDValue RHS = Op.getOperand(3);
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SDValue Dest = Op.getOperand(4);
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DebugLoc dl = Op.getDebugLoc();
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SDValue SystemZCC;
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SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
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return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
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Chain, Dest, SystemZCC, Flag);
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}
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const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
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case SystemZISD::CALL: return "SystemZISD::CALL";
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case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
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case SystemZISD::CMP: return "SystemZISD::CMP";
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case SystemZISD::UCMP: return "SystemZISD::UCMP";
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default: return NULL;
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}
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}
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@ -30,7 +30,11 @@ namespace llvm {
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/// CALL/TAILCALL - These operations represent an abstract call
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/// instruction, which includes a bunch of information.
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CALL
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CALL,
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CMP,
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UCMP,
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BRCOND
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};
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}
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@ -51,14 +55,18 @@ namespace llvm {
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SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
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SDValue LowerRET(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCArguments(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC);
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SDNode* LowerCallResult(SDValue Chain, SDValue InFlag,
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CallSDNode *TheCall,
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unsigned CallingConv, SelectionDAG &DAG);
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SDValue EmitCmp(SDValue LHS, SDValue RHS,
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ISD::CondCode CC, SDValue &SystemZCC,
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SelectionDAG &DAG);
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private:
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const SystemZSubtarget &Subtarget;
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const SystemZTargetMachine &TM;
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@ -27,6 +27,10 @@ class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
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def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>;
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def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
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def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
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def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def SDT_BrCond : SDTypeProfile<0, 2,
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[SDTCisVT<0, OtherVT>,
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SDTCisI8<1>]>;
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//===----------------------------------------------------------------------===//
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// SystemZ Specific Node Definitions.
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@ -41,10 +45,24 @@ def SystemZcallseq_start :
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def SystemZcallseq_end :
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SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
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def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
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def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
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[SDNPHasChain, SDNPInFlag]>;
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//===----------------------------------------------------------------------===//
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// Instruction Pattern Stuff.
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//===----------------------------------------------------------------------===//
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// SystemZ specific condition code. These correspond to CondCode in
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// SystemZ.h. They must be kept in synch.
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def SYSTEMZ_COND_E : PatLeaf<(i8 0)>;
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def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
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def SYSTEMZ_COND_H : PatLeaf<(i8 2)>;
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def SYSTEMZ_COND_L : PatLeaf<(i8 3)>;
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def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
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def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
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def LL16 : SDNodeXForm<imm, [{
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// Transformation function: return low 16 bits.
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return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
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@ -140,6 +158,18 @@ def i32immSExt16 : PatLeaf<(i32 imm), [{
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return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
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}]>;
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def i64immSExt32 : PatLeaf<(i64 imm), [{
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// i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// sign extended field.
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return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
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}]>;
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def i64immZExt32 : PatLeaf<(i64 imm), [{
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// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
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// zero extended field.
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return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
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}]>;
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// extloads
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def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
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def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
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@ -158,6 +188,10 @@ def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
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def i32i8imm : Operand<i32>;
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// 32-bits but only 16 bits are significant.
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def i32i16imm : Operand<i32>;
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// 64-bits but only 32 bits are significant.
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def i64i32imm : Operand<i64>;
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// Branch targets have OtherVT type.
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def brtarget : Operand<OtherVT>;
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//===----------------------------------------------------------------------===//
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// SystemZ Operand Definitions.
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@ -208,10 +242,34 @@ def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
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//
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// FIXME: Provide proper encoding!
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let isReturn = 1, isTerminator = 1 in {
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let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
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def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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let Uses = [PSW] in {
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def JE : Pseudo<(outs), (ins brtarget:$dst),
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"je\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
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def JNE : Pseudo<(outs), (ins brtarget:$dst),
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"jne\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
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def JH : Pseudo<(outs), (ins brtarget:$dst),
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"jh\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
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def JL : Pseudo<(outs), (ins brtarget:$dst),
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"jl\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
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def JHE : Pseudo<(outs), (ins brtarget:$dst),
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"jhe\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
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def JLE : Pseudo<(outs), (ins brtarget:$dst),
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"jle\t$dst",
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[(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
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} // Uses = [PSW]
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} // isBranch = 1
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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@ -560,6 +618,81 @@ def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
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(implicit PSW)]>;
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} // Defs = [PSW]
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//===----------------------------------------------------------------------===//
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// Test instructions (like AND but do not produce any result
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// Integer comparisons
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let Defs = [PSW] in {
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def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
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"cr\t$src1, $src2",
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[(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
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def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
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"cgr\t$src1, $src2",
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[(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
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def CMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
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"cfi\t$src1, $src2",
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[(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
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def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
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"cgfi\t$src1, $src2",
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[(SystemZcmp GR64:$src1, i64immSExt32:$src2),
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(implicit PSW)]>;
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def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
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"cy\t$src1, $src2",
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[(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
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(implicit PSW)]>;
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def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
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"cg\t$src1, $src2",
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[(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
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(implicit PSW)]>;
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def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
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"clr\t$src1, $src2",
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[(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
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def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
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"clgr\t$src1, $src2",
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[(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
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def UCMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
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"clfi\t$src1, $src2",
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[(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
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def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
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"clgfi\t$src1, $src2",
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[(SystemZucmp GR64:$src1, i64immZExt32:$src2),
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(implicit PSW)]>;
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def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
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"cly\t$src1, $src2",
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[(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
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(implicit PSW)]>;
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def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
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"clg\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
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(implicit PSW)]>;
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def CMPSX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
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"cgfr\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (sext GR32:$src2)),
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(implicit PSW)]>;
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def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
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"clgfr\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (zext GR32:$src2)),
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(implicit PSW)]>;
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def CMPSX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
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"cgf\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
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(implicit PSW)]>;
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def UCMPZX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
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"clgf\t$src1, $src2",
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[(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
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(implicit PSW)]>;
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// FIXME: Add other crazy ucmp forms
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} // Defs = [PSW]
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns.
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//===----------------------------------------------------------------------===//
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