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Code Issues Projects Releases Wiki Activity

Have TargetRegisterInfo::getLargestLegalSuperClass take a

Browse Source 
MachineFunction argument so that it can look up the subtarget
rather than using a cached one in some Targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231888 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-03-10 23:46:01 +00:00
parent b8de3287ee
commit 4ec858ec4b
13 changed files with 33 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/llvm/Target/TargetRegisterInfo.h
View File

@ -622,8 +622,9 @@ public:
/// legal to use in the current sub-target and has the same spill size.
/// The returned register class can be used to create virtual registers which
/// means that all its registers can be copied and spilled.
virtual const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
virtual const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &) const {
/// The default implementation is very conservative and doesn't allow the
/// register allocator to inflate register classes.
return RC;

2
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -65,7 +65,7 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
const TargetRegisterClass *OldRC = getRegClass(Reg);
const TargetRegisterClass *NewRC =
getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC, *MF);
// Stop early if there is no room to grow.
if (NewRC == OldRC)

2
lib/CodeGen/MachineVerifier.cpp
View File

@ -927,7 +927,7 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
TII->getRegClass(MCID, MONum, TRI, *MF)) {
if (SubIdx) {
const TargetRegisterClass *SuperRC =
TRI->getLargestLegalSuperClass(RC);
TRI->getLargestLegalSuperClass(RC, *MF);
if (!SuperRC) {
report("No largest legal super class exists.", MO, MONum);
return;

3
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -1554,7 +1554,8 @@ RAGreedy::tryInstructionSplit(LiveInterval &VirtReg, AllocationOrder &Order,
DEBUG(dbgs() << "Split around " << Uses.size() << " individual instrs.\n");
const TargetRegisterClass *SuperRC = TRI->getLargestLegalSuperClass(CurRC);
const TargetRegisterClass *SuperRC =
TRI->getLargestLegalSuperClass(CurRC, *MF);
unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
// Split around every non-copy instruction if this split will relax
// the constraints on the virtual register.

3
lib/CodeGen/RegisterClassInfo.cpp
View File

@ -131,7 +131,8 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
RCI.NumRegs = StressRA;
// Check if RC is a proper sub-class.
if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
if (const TargetRegisterClass *Super =
TRI->getLargestLegalSuperClass(RC, *MF))
if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
RCI.ProperSubClass = true;

6
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -150,9 +150,9 @@ getReservedRegs(const MachineFunction &MF) const {
return Reserved;
}
const TargetRegisterClass*
ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
const {
const TargetRegisterClass *
ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &) const {
const TargetRegisterClass *Super = RC;
TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
do {

3
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -124,7 +124,8 @@ public:
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;

8
lib/Target/ARM/Thumb1RegisterInfo.cpp
View File

@ -42,12 +42,12 @@ Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMSubtarget &sti)
: ARMBaseRegisterInfo(sti) {
}
const TargetRegisterClass*
Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
const {
const TargetRegisterClass *
Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
if (ARM::tGPRRegClass.hasSubClassEq(RC))
return &ARM::tGPRRegClass;
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC, MF);
}
const TargetRegisterClass *

3
lib/Target/ARM/Thumb1RegisterInfo.h
View File

@ -27,7 +27,8 @@ public:
Thumb1RegisterInfo(const ARMSubtarget &STI);
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const override;
const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF,

7
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -288,8 +288,9 @@ unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
}
}
const TargetRegisterClass *PPCRegisterInfo::getLargestLegalSuperClass(
const TargetRegisterClass *RC) const {
const TargetRegisterClass *
PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
if (Subtarget.hasVSX()) {
// With VSX, we can inflate various sub-register classes to the full VSX
// register set.
@ -300,7 +301,7 @@ const TargetRegisterClass *PPCRegisterInfo::getLargestLegalSuperClass(
return &PPC::VSRCRegClass;
}
return TargetRegisterInfo::getLargestLegalSuperClass(RC);
return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
}
//===----------------------------------------------------------------------===//

5
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -40,8 +40,9 @@ public:
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const override;
/// Code Generation virtual methods...
const MCPhysReg *

5
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -120,8 +120,9 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return X86GenRegisterInfo::getMatchingSuperRegClass(A, B, SubIdx);
}
const TargetRegisterClass*
X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
const TargetRegisterClass *
X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
// Don't allow super-classes of GR8_NOREX. This class is only used after
// extracting sub_8bit_hi sub-registers. The H sub-registers cannot be copied
// to the full GR8 register class in 64-bit mode, so we cannot allow the

5
lib/Target/X86/X86RegisterInfo.h
View File

@ -76,8 +76,9 @@ public:
getSubClassWithSubReg(const TargetRegisterClass *RC,
unsigned Idx) const override;
const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const override;
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
/// values.