From 4ec9bd9a6f92a10185870bae2cebce199f6acc5a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 25 Mar 2010 07:16:57 +0000 Subject: [PATCH] Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99501 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 07dcc0e4f13..e7ab2f00396 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -528,8 +528,16 @@ EmitSchedule(DenseMap *EM) { if (!MI) continue; MachineBasicBlock *MIBB = MI->getParent(); +#ifndef NDEBUG + unsigned LastDIOrder = 0; +#endif for (; DI != DE && (*DI)->getOrder() >= LastOrder && (*DI)->getOrder() < Order; ++DI) { +#ifndef NDEBUG + assert((*DI)->getOrder() >= LastDIOrder && + "SDDbgValue nodes must be in source order!"); + LastDIOrder = (*DI)->getOrder(); +#endif if ((*DI)->isInvalidated()) continue; MachineInstr *DbgMI = Emitter.EmitDbgValue(*DI, MIBB, VRBaseMap, EM);