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Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.

Browse Source 
The main advantages here are way better heuristics, taking into account not
just loop depth but also __builtin_expect and other static heuristics and will
eventually learn how to use profile info. Most of the work in this patch is
pushing the MachineBlockFrequencyInfo analysis into the right places.

This is good for a 5% speedup on zlib's deflate (x86_64), there were some very
unfortunate spilling decisions in its hottest loop in longest_match(). Other
benchmarks I tried were mostly neutral.

This changes register allocation in subtle ways, update the tests for it.
2012-02-20-MachineCPBug.ll was deleted as it's very fragile and the instruction
it looked for was gone already (but the FileCheck pattern picked up unrelated
stuff).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184105 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-06-17 19:00:36 +00:00
parent a8a04380c5
commit 4eed756153
19 changed files with 84 additions and 144 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/llvm/CodeGen/CalcSpillWeights.h
View File

@ -18,6 +18,7 @@ namespace llvm {
class LiveInterval;
class LiveIntervals;
class MachineBlockFrequencyInfo;
class MachineLoopInfo;
/// normalizeSpillWeight - The spill weight of a live interval is computed as:
@ -43,11 +44,13 @@ namespace llvm {
MachineFunction &MF;
LiveIntervals &LIS;
const MachineLoopInfo &Loops;
const MachineBlockFrequencyInfo &MBFI;
DenseMap<unsigned, float> Hint;
public:
VirtRegAuxInfo(MachineFunction &mf, LiveIntervals &lis,
const MachineLoopInfo &loops) :
MF(mf), LIS(lis), Loops(loops) {}
const MachineLoopInfo &loops,
const MachineBlockFrequencyInfo &mbfi)
: MF(mf), LIS(lis), Loops(loops), MBFI(mbfi) {}
/// CalculateWeightAndHint - (re)compute li's spill weight and allocation
/// hint.

3
include/llvm/CodeGen/LiveIntervalAnalysis.h
View File

@ -35,6 +35,7 @@ namespace llvm {
class AliasAnalysis;
class BitVector;
class BlockFrequency;
class LiveRangeCalc;
class LiveVariables;
class MachineDominatorTree;
@ -99,7 +100,7 @@ namespace llvm {
virtual ~LiveIntervals();
// Calculate the spill weight to assign to a single instruction.
static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
static float getSpillWeight(bool isDef, bool isUse, BlockFrequency freq);
LiveInterval &getInterval(unsigned Reg) {
LiveInterval *LI = VirtRegIntervals[Reg];

4
include/llvm/CodeGen/LiveRangeEdit.h
View File

@ -27,6 +27,7 @@ namespace llvm {
class AliasAnalysis;
class LiveIntervals;
class MachineBlockFrequencyInfo;
class MachineLoopInfo;
class MachineRegisterInfo;
class VirtRegMap;
@ -201,7 +202,8 @@ public:
/// calculateRegClassAndHint - Recompute register class and hint for each new
/// register.
void calculateRegClassAndHint(MachineFunction&,
const MachineLoopInfo&);
const MachineLoopInfo&,
const MachineBlockFrequencyInfo&);
};
}

6
include/llvm/CodeGen/RegAllocPBQP.h
View File

@ -26,8 +26,8 @@
namespace llvm {
class LiveIntervals;
class MachineBlockFrequencyInfo;
class MachineFunction;
class MachineLoopInfo;
class TargetRegisterInfo;
template<class T> class OwningPtr;
@ -125,7 +125,7 @@ namespace llvm {
/// Build a PBQP instance to represent the register allocation problem for
/// the given MachineFunction.
virtual PBQPRAProblem *build(MachineFunction *mf, const LiveIntervals *lis,
const MachineLoopInfo *loopInfo,
const MachineBlockFrequencyInfo *mbfi,
const RegSet &vregs);
private:
@ -144,7 +144,7 @@ namespace llvm {
/// Build a PBQP instance to represent the register allocation problem for
/// the given MachineFunction.
virtual PBQPRAProblem *build(MachineFunction *mf, const LiveIntervals *lis,
const MachineLoopInfo *loopInfo,
const MachineBlockFrequencyInfo *mbfi,
const RegSet &vregs);
private:

13
lib/CodeGen/CalcSpillWeights.cpp
View File

@ -12,6 +12,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@ -33,6 +34,7 @@ INITIALIZE_PASS_END(CalculateSpillWeights, "calcspillweights",
void CalculateSpillWeights::getAnalysisUsage(AnalysisUsage &au) const {
au.addRequired<LiveIntervals>();
au.addRequired<MachineBlockFrequencyInfo>();
au.addRequired<MachineLoopInfo>();
au.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(au);
@ -45,7 +47,8 @@ bool CalculateSpillWeights::runOnMachineFunction(MachineFunction &MF) {
LiveIntervals &LIS = getAnalysis<LiveIntervals>();
MachineRegisterInfo &MRI = MF.getRegInfo();
VirtRegAuxInfo VRAI(MF, LIS, getAnalysis<MachineLoopInfo>());
VirtRegAuxInfo VRAI(MF, LIS, getAnalysis<MachineLoopInfo>(),
getAnalysis<MachineBlockFrequencyInfo>());
for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
if (MRI.reg_nodbg_empty(Reg))
@ -107,12 +110,12 @@ static bool isRematerializable(const LiveInterval &LI,
return true;
}
void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
void
VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
MachineRegisterInfo &mri = MF.getRegInfo();
const TargetRegisterInfo &tri = *MF.getTarget().getRegisterInfo();
MachineBasicBlock *mbb = 0;
MachineLoop *loop = 0;
unsigned loopDepth = 0;
bool isExiting = false;
float totalWeight = 0;
SmallPtrSet<MachineInstr*, 8> visited;
@ -140,14 +143,14 @@ void VirtRegAuxInfo::CalculateWeightAndHint(LiveInterval &li) {
if (mi->getParent() != mbb) {
mbb = mi->getParent();
loop = Loops.getLoopFor(mbb);
loopDepth = loop ? loop->getLoopDepth() : 0;
isExiting = loop ? loop->isLoopExiting(mbb) : false;
}
// Calculate instr weight.
bool reads, writes;
tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
weight = LiveIntervals::getSpillWeight(writes, reads, loopDepth);
weight = LiveIntervals::getSpillWeight(
writes, reads, MBFI.getBlockFreq(mi->getParent()));
// Give extra weight to what looks like a loop induction variable update.
if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb))

7
lib/CodeGen/InlineSpiller.cpp
View File

@ -22,6 +22,7 @@
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
@ -65,6 +66,7 @@ class InlineSpiller : public Spiller {
MachineRegisterInfo &MRI;
const TargetInstrInfo &TII;
const TargetRegisterInfo &TRI;
const MachineBlockFrequencyInfo &MBFI;
// Variables that are valid during spill(), but used by multiple methods.
LiveRangeEdit *Edit;
@ -148,7 +150,8 @@ public:
MFI(*mf.getFrameInfo()),
MRI(mf.getRegInfo()),
TII(*mf.getTarget().getInstrInfo()),
TRI(*mf.getTarget().getRegisterInfo()) {}
TRI(*mf.getTarget().getRegisterInfo()),
MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()) {}
void spill(LiveRangeEdit &);
@ -1290,5 +1293,5 @@ void InlineSpiller::spill(LiveRangeEdit &edit) {
if (!RegsToSpill.empty())
spillAll();
Edit->calculateRegClassAndHint(MF, Loops);
Edit->calculateRegClassAndHint(MF, Loops, MBFI);
}

19
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -28,6 +28,7 @@
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Value.h"
#include "llvm/Support/BlockFrequency.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
@ -605,21 +606,9 @@ LiveIntervals::hasPHIKill(const LiveInterval &LI, const VNInfo *VNI) const {
}
float
LiveIntervals::getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
// Limit the loop depth ridiculousness.
if (loopDepth > 200)
loopDepth = 200;
// The loop depth is used to roughly estimate the number of times the
// instruction is executed. Something like 10^d is simple, but will quickly
// overflow a float. This expression behaves like 10^d for small d, but is
// more tempered for large d. At d=200 we get 6.7e33 which leaves a bit of
// headroom before overflow.
// By the way, powf() might be unavailable here. For consistency,
// We may take pow(double,double).
float lc = std::pow(1 + (100.0 / (loopDepth + 10)), (double)loopDepth);
return (isDef + isUse) * lc;
LiveIntervals::getSpillWeight(bool isDef, bool isUse, BlockFrequency freq) {
const float Scale = 1.0f / BlockFrequency::getEntryFrequency();
return (isDef + isUse) * (freq.getFrequency() * Scale);
}
LiveRange LiveIntervals::addLiveRangeToEndOfBlock(unsigned reg,

8
lib/CodeGen/LiveRangeEdit.cpp
View File

@ -374,9 +374,11 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
}
}
void LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
const MachineLoopInfo &Loops) {
VirtRegAuxInfo VRAI(MF, LIS, Loops);
void
LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
const MachineLoopInfo &Loops,
const MachineBlockFrequencyInfo &MBFI) {
VirtRegAuxInfo VRAI(MF, LIS, Loops, MBFI);
for (iterator I = begin(), E = end(); I != E; ++I) {
LiveInterval &LI = **I;
if (MRI.recomputeRegClass(LI.reg, MF.getTarget()))

3
lib/CodeGen/RegAllocBasic.cpp
View File

@ -24,6 +24,7 @@
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
@ -145,6 +146,8 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<CalculateSpillWeights>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();
AU.addRequired<MachineBlockFrequencyInfo>();
AU.addPreserved<MachineBlockFrequencyInfo>();
AU.addRequiredID(MachineDominatorsID);
AU.addPreservedID(MachineDominatorsID);
AU.addRequired<MachineLoopInfo>();

7
lib/CodeGen/RegAllocGreedy.cpp
View File

@ -29,6 +29,7 @@
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
@ -71,6 +72,7 @@ class RAGreedy : public MachineFunctionPass,
// analyses
SlotIndexes *Indexes;
MachineBlockFrequencyInfo *MBFI;
MachineDominatorTree *DomTree;
MachineLoopInfo *Loops;
EdgeBundles *Bundles;
@ -320,6 +322,8 @@ RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineBlockFrequencyInfo>();
AU.addPreserved<MachineBlockFrequencyInfo>();
AU.addRequired<AliasAnalysis>();
AU.addPreserved<AliasAnalysis>();
AU.addRequired<LiveIntervals>();
@ -1770,6 +1774,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
getAnalysis<LiveIntervals>(),
getAnalysis<LiveRegMatrix>());
Indexes = &getAnalysis<SlotIndexes>();
MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
DomTree = &getAnalysis<MachineDominatorTree>();
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));
Loops = &getAnalysis<MachineLoopInfo>();
@ -1778,7 +1783,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
DebugVars = &getAnalysis<LiveDebugVariables>();
SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops));
SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree));
SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree, *MBFI));
ExtraRegInfo.clear();
ExtraRegInfo.resize(MRI->getNumVirtRegs());
NextCascade = 1;

21
lib/CodeGen/RegAllocPBQP.cpp
View File

@ -40,9 +40,9 @@
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PBQP/Graph.h"
#include "llvm/CodeGen/PBQP/HeuristicSolver.h"
@ -96,7 +96,6 @@ public:
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
}
@ -130,8 +129,8 @@ private:
const TargetMachine *tm;
const TargetRegisterInfo *tri;
const TargetInstrInfo *tii;
const MachineLoopInfo *loopInfo;
MachineRegisterInfo *mri;
const MachineBlockFrequencyInfo *mbfi;
OwningPtr<Spiller> spiller;
LiveIntervals *lis;
@ -188,7 +187,7 @@ unsigned PBQPRAProblem::getPRegForOption(unsigned vreg, unsigned option) const {
}
PBQPRAProblem *PBQPBuilder::build(MachineFunction *mf, const LiveIntervals *lis,
const MachineLoopInfo *loopInfo,
const MachineBlockFrequencyInfo *mbfi,
const RegSet &vregs) {
LiveIntervals *LIS = const_cast<LiveIntervals*>(lis);
@ -313,10 +312,10 @@ void PBQPBuilder::addInterferenceCosts(
PBQPRAProblem *PBQPBuilderWithCoalescing::build(MachineFunction *mf,
const LiveIntervals *lis,
const MachineLoopInfo *loopInfo,
const MachineBlockFrequencyInfo *mbfi,
const RegSet &vregs) {
OwningPtr<PBQPRAProblem> p(PBQPBuilder::build(mf, lis, loopInfo, vregs));
OwningPtr<PBQPRAProblem> p(PBQPBuilder::build(mf, lis, mbfi, vregs));
PBQP::Graph &g = p->getGraph();
const TargetMachine &tm = mf->getTarget();
@ -350,7 +349,7 @@ PBQPRAProblem *PBQPBuilderWithCoalescing::build(MachineFunction *mf,
PBQP::PBQPNum cBenefit =
copyFactor * LiveIntervals::getSpillWeight(false, true,
loopInfo->getLoopDepth(mbb));
mbfi->getBlockFreq(mbb));
if (cp.isPhys()) {
if (!mf->getRegInfo().isAllocatable(dst)) {
@ -435,10 +434,10 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
au.addRequired<CalculateSpillWeights>();
au.addRequired<LiveStacks>();
au.addPreserved<LiveStacks>();
au.addRequired<MachineBlockFrequencyInfo>();
au.addPreserved<MachineBlockFrequencyInfo>();
au.addRequired<MachineDominatorTree>();
au.addPreserved<MachineDominatorTree>();
au.addRequired<MachineLoopInfo>();
au.addPreserved<MachineLoopInfo>();
au.addRequired<VirtRegMap>();
au.addPreserved<VirtRegMap>();
MachineFunctionPass::getAnalysisUsage(au);
@ -546,7 +545,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
lis = &getAnalysis<LiveIntervals>();
lss = &getAnalysis<LiveStacks>();
loopInfo = &getAnalysis<MachineLoopInfo>();
mbfi = &getAnalysis<MachineBlockFrequencyInfo>();
vrm = &getAnalysis<VirtRegMap>();
spiller.reset(createInlineSpiller(*this, MF, *vrm));
@ -584,7 +583,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << " PBQP Regalloc round " << round << ":\n");
OwningPtr<PBQPRAProblem> problem(
builder->build(mf, lis, loopInfo, vregsToAlloc));
builder->build(mf, lis, mbfi, vregsToAlloc));
#ifndef NDEBUG
if (pbqpDumpGraphs) {

8
lib/CodeGen/SpillPlacement.cpp
View File

@ -31,8 +31,8 @@
#include "SpillPlacement.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/CodeGen/EdgeBundles.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
@ -53,6 +53,7 @@ char &llvm::SpillPlacementID = SpillPlacement::ID;
void SpillPlacement::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
AU.addRequired<MachineBlockFrequencyInfo>();
AU.addRequiredTransitive<EdgeBundles>();
AU.addRequiredTransitive<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
@ -178,9 +179,10 @@ bool SpillPlacement::runOnMachineFunction(MachineFunction &mf) {
// Compute total ingoing and outgoing block frequencies for all bundles.
BlockFrequency.resize(mf.getNumBlockIDs());
MachineBlockFrequencyInfo &MBFI = getAnalysis<MachineBlockFrequencyInfo>();
float EntryFreq = BlockFrequency::getEntryFrequency();
for (MachineFunction::iterator I = mf.begin(), E = mf.end(); I != E; ++I) {
float Freq = LiveIntervals::getSpillWeight(true, false,
loops->getLoopDepth(I));
float Freq = MBFI.getBlockFreq(I).getFrequency() / EntryFreq;
unsigned Num = I->getNumber();
BlockFrequency[Num] = Freq;
nodes[bundles->getBundle(Num, 1)].Scale[0] += Freq;

6
lib/CodeGen/SplitKit.cpp
View File

@ -325,12 +325,14 @@ void SplitAnalysis::analyze(const LiveInterval *li) {
SplitEditor::SplitEditor(SplitAnalysis &sa,
LiveIntervals &lis,
VirtRegMap &vrm,
MachineDominatorTree &mdt)
MachineDominatorTree &mdt,
MachineBlockFrequencyInfo &mbfi)
: SA(sa), LIS(lis), VRM(vrm),
MRI(vrm.getMachineFunction().getRegInfo()),
MDT(mdt),
TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
MBFI(mbfi),
Edit(0),
OpenIdx(0),
SpillMode(SM_Partition),
@ -1119,7 +1121,7 @@ void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
}
// Calculate spill weight and allocation hints for new intervals.
Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops);
Edit->calculateRegClassAndHint(VRM.getMachineFunction(), SA.Loops, MBFI);
assert(!LRMap || LRMap->size() == Edit->size());
}

4
lib/CodeGen/SplitKit.h
View File

@ -27,6 +27,7 @@ class ConnectedVNInfoEqClasses;
class LiveInterval;
class LiveIntervals;
class LiveRangeEdit;
class MachineBlockFrequencyInfo;
class MachineInstr;
class MachineLoopInfo;
class MachineRegisterInfo;
@ -215,6 +216,7 @@ class SplitEditor {
MachineDominatorTree &MDT;
const TargetInstrInfo &TII;
const TargetRegisterInfo &TRI;
const MachineBlockFrequencyInfo &MBFI;
public:
@ -349,7 +351,7 @@ public:
/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
/// Newly created intervals will be appended to newIntervals.
SplitEditor(SplitAnalysis &SA, LiveIntervals&, VirtRegMap&,
MachineDominatorTree&);
MachineDominatorTree&, MachineBlockFrequencyInfo &);
/// reset - Prepare for a new split.
void reset(LiveRangeEdit&, ComplementSpillMode = SM_Partition);

14
lib/CodeGen/StackSlotColoring.cpp
View File

@ -19,9 +19,9 @@
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
@ -48,7 +48,7 @@ namespace {
LiveStacks* LS;
MachineFrameInfo *MFI;
const TargetInstrInfo *TII;
const MachineLoopInfo *loopInfo;
const MachineBlockFrequencyInfo *MBFI;
// SSIntervals - Spill slot intervals.
std::vector<LiveInterval*> SSIntervals;
@ -89,8 +89,8 @@ namespace {
AU.addRequired<SlotIndexes>();
AU.addPreserved<SlotIndexes>();
AU.addRequired<LiveStacks>();
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>();
AU.addRequired<MachineBlockFrequencyInfo>();
AU.addPreserved<MachineBlockFrequencyInfo>();
AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU);
}
@ -139,7 +139,7 @@ void StackSlotColoring::ScanForSpillSlotRefs(MachineFunction &MF) {
for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
MBBI != E; ++MBBI) {
MachineBasicBlock *MBB = &*MBBI;
unsigned loopDepth = loopInfo->getLoopDepth(MBB);
BlockFrequency Freq = MBFI->getBlockFreq(MBB);
for (MachineBasicBlock::iterator MII = MBB->begin(), EE = MBB->end();
MII != EE; ++MII) {
MachineInstr *MI = &*MII;
@ -154,7 +154,7 @@ void StackSlotColoring::ScanForSpillSlotRefs(MachineFunction &MF) {
continue;
LiveInterval &li = LS->getInterval(FI);
if (!MI->isDebugValue())
li.weight += LiveIntervals::getSpillWeight(false, true, loopDepth);
li.weight += LiveIntervals::getSpillWeight(false, true, Freq);
SSRefs[FI].push_back(MI);
}
}
@ -396,7 +396,7 @@ bool StackSlotColoring::runOnMachineFunction(MachineFunction &MF) {
MFI = MF.getFrameInfo();
TII = MF.getTarget().getInstrInfo();
LS = &getAnalysis<LiveStacks>();
loopInfo = &getAnalysis<MachineLoopInfo>();
MBFI = &getAnalysis<MachineBlockFrequencyInfo>();
bool Changed = false;

3
test/CodeGen/ARM/lsr-unfolded-offset.ll
View File

@ -7,8 +7,7 @@
; CHECK: sub sp, #{{40|32|28|24}}
; CHECK: %for.inc
; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, #
; CHECK-NOT: ldr
; CHECK: add
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"

2
test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
View File

@ -59,7 +59,7 @@ entry:
;CHECK: !NO_APP
;CHECK-NEXT: cmp
;CHECK-NEXT: bg
;CHECK-NEXT: nop
;CHECK-NEXT: or
tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
%0 = icmp slt i32 %a, 0
br i1 %0, label %bb, label %bb1

78
test/CodeGen/X86/2012-02-20-MachineCPBug.ll
View File

@ -1,78 +0,0 @@
; RUN: llc < %s -mtriple=i386-apple-macosx -mcpu=core2 -mattr=+sse | FileCheck %s
; PR11940: Do not optimize away movb %al, %ch
%struct.APInt = type { i64* }
declare noalias i8* @calloc(i32, i32) nounwind
define void @bug(%struct.APInt* noalias nocapture sret %agg.result, %struct.APInt* nocapture %this, i32 %rotateAmt) nounwind align 2 {
entry:
; CHECK: bug:
%call = tail call i8* @calloc(i32 1, i32 32)
%call.i = tail call i8* @calloc(i32 1, i32 32) nounwind
%0 = bitcast i8* %call.i to i64*
%rem.i = and i32 %rotateAmt, 63
%div.i = lshr i32 %rotateAmt, 6
%cmp.i = icmp eq i32 %rem.i, 0
br i1 %cmp.i, label %for.cond.preheader.i, label %if.end.i
for.cond.preheader.i: ; preds = %entry
%sub.i = sub i32 4, %div.i
%cmp23.i = icmp eq i32 %div.i, 4
br i1 %cmp23.i, label %for.body9.lr.ph.i, label %for.body.lr.ph.i
for.body.lr.ph.i: ; preds = %for.cond.preheader.i
%pVal.i = getelementptr inbounds %struct.APInt* %this, i32 0, i32 0
%.pre5.i = load i64** %pVal.i, align 4
br label %for.body.i
for.body.i: ; preds = %for.body.i, %for.body.lr.ph.i
%i.04.i = phi i32 [ 0, %for.body.lr.ph.i ], [ %inc.i, %for.body.i ]
%add.i = add i32 %i.04.i, %div.i
%arrayidx.i = getelementptr inbounds i64* %.pre5.i, i32 %add.i
%1 = load i64* %arrayidx.i, align 4
%arrayidx3.i = getelementptr inbounds i64* %0, i32 %i.04.i
store i64 %1, i64* %arrayidx3.i, align 4
%inc.i = add i32 %i.04.i, 1
%cmp2.i = icmp ult i32 %inc.i, %sub.i
br i1 %cmp2.i, label %for.body.i, label %if.end.i
if.end.i: ; preds = %for.body.i, %entry
%cmp81.i = icmp eq i32 %div.i, 3
br i1 %cmp81.i, label %_ZNK5APInt4lshrEj.exit, label %for.body9.lr.ph.i
for.body9.lr.ph.i: ; preds = %if.end.i, %for.cond.preheader.i
%sub58.i = sub i32 3, %div.i
%pVal11.i = getelementptr inbounds %struct.APInt* %this, i32 0, i32 0
%sh_prom.i = zext i32 %rem.i to i64
%sub17.i = sub i32 64, %rem.i
%sh_prom18.i = zext i32 %sub17.i to i64
%.pre.i = load i64** %pVal11.i, align 4
br label %for.body9.i
for.body9.i: ; preds = %for.body9.i, %for.body9.lr.ph.i
; CHECK: %for.body9.i
; CHECK: movb
; CHECK: shrdl
%i6.02.i = phi i32 [ 0, %for.body9.lr.ph.i ], [ %inc21.i, %for.body9.i ]
%add10.i = add i32 %i6.02.i, %div.i
%arrayidx12.i = getelementptr inbounds i64* %.pre.i, i32 %add10.i
%2 = load i64* %arrayidx12.i, align 4
%shr.i = lshr i64 %2, %sh_prom.i
%add14.i = add i32 %add10.i, 1
%arrayidx16.i = getelementptr inbounds i64* %.pre.i, i32 %add14.i
%3 = load i64* %arrayidx16.i, align 4
%shl.i = shl i64 %3, %sh_prom18.i
%or.i = or i64 %shl.i, %shr.i
%arrayidx19.i = getelementptr inbounds i64* %0, i32 %i6.02.i
store i64 %or.i, i64* %arrayidx19.i, align 4
%inc21.i = add i32 %i6.02.i, 1
%cmp8.i = icmp ult i32 %inc21.i, %sub58.i
br i1 %cmp8.i, label %for.body9.i, label %_ZNK5APInt4lshrEj.exit
_ZNK5APInt4lshrEj.exit: ; preds = %for.body9.i, %if.end.i
%call.i1 = tail call i8* @calloc(i32 1, i32 32) nounwind
%4 = getelementptr inbounds %struct.APInt* %agg.result, i32 0, i32 0
store i64* %0, i64** %4, align 4
ret void
}

15
test/CodeGen/X86/atom-bypass-slow-division-64.ll
View File

@ -4,8 +4,9 @@
define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
; CHECK: Test_get_quotient:
; CHECK: orq %rsi, %rcx
; CHECK-NEXT: testq $-65536, %rcx
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; CHECK-NEXT: je
; CHECK: idivq
; CHECK: ret
@ -17,8 +18,9 @@ define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
; CHECK: Test_get_remainder:
; CHECK: orq %rsi, %rcx
; CHECK-NEXT: testq $-65536, %rcx
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; CHECK-NEXT: je
; CHECK: idivq
; CHECK: ret
@ -30,8 +32,9 @@ define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
; CHECK: Test_get_quotient_and_remainder:
; CHECK: orq %rsi, %rcx
; CHECK-NEXT: testq $-65536, %rcx
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; CHECK-NEXT: je
; CHECK: idivq
; CHECK: divw