6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-19 19:29:31 +00:00
Code Issues Projects Releases Wiki Activity

Rather than attempting to legalize 1 x float, make sure the SD ISel never

Browse Source 
generates it.  Make MVT::Vector expand-only, and remove the code in
Legalize that attempts to legalize it.

The plan for supporting N x Type is to continually epxand it in ExpandOp
until it gets down to 2 x Type, where it will be scalarized into a pair of
scalars.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24482 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-11-22 01:29:36 +00:00
parent ac2902bcb5
commit 4ef3b817fe
3 changed files with 29 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -925,26 +925,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
case ISD::VLOAD:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
// If we just have one element, scalarize the result. Otherwise, check to
// see if we support this operation on this type at this width. If not,
// split the vector in half and try again.
if (1 == cast<ConstantSDNode>(Node->getOperand(2))->getValue()) {
MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
Result = LegalizeOp(DAG.getLoad(SVT, Tmp1, Tmp2, Node->getOperand(4)));
} else {
assert(0 && "Expand case for vectors unimplemented");
}
// Since loads produce two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result);
AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
return Result.getValue(Op.ResNo);
case ISD::EXTLOAD:
case ISD::SEXTLOAD:
case ISD::ZEXTLOAD: {
@ -1685,28 +1665,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
break;
// Vector binary operators
case ISD::VADD:
case ISD::VSUB:
case ISD::VMUL: {
Tmp1 = Node->getOperand(0); // Element Count
Tmp2 = Node->getOperand(1); // Element Type
// If we just have one element, scalarize the result. Otherwise, check to
// see if we support this operation on this type at this width. If not,
// split the vector in half and try again.
if (1 == cast<ConstantSDNode>(Tmp1)->getValue()) {
MVT::ValueType SVT = cast<VTSDNode>(Tmp2)->getVT();
Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), SVT), SVT,
LegalizeOp(Node->getOperand(2)),
LegalizeOp(Node->getOperand(3)));
} else {
assert(0 && "Expand case for vectors unimplemented");
}
break;
}
case ISD::BUILD_PAIR: {
MVT::ValueType PairTy = Node->getValueType(0);
// TODO: handle the case where the Lo and Hi operands are not of legal type

30
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -517,9 +517,19 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
} else {
const PackedType *PTy = cast<PackedType>(Ty);
SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
setValue(&I, DAG.getNode(VecOp, Op1.getValueType(), Num, Typ, Op1, Op2));
unsigned NumElements = PTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
// Immediately scalarize packed types containing only one element, so that
// the Legalize pass does not have to deal with them.
if (NumElements == 1) {
unsigned Opc = MVT::isFloatingPoint(PVT) ? FPOp : IntOp;
setValue(&I, DAG.getNode(Opc, PVT, Op1, Op2));
} else {
SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
SDOperand Typ = DAG.getValueType(PVT);
setValue(&I, DAG.getNode(VecOp, Op1.getValueType(), Num, Typ, Op1, Op2));
}
}
}
@ -726,9 +736,17 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
if (Type::PackedTyID == Ty->getTypeID()) {
const PackedType *PTy = cast<PackedType>(Ty);
L = DAG.getVecLoad(PTy->getNumElements(),
TLI.getValueType(PTy->getElementType()), Root, Ptr,
DAG.getSrcValue(I.getOperand(0)));
unsigned NumElements = PTy->getNumElements();
MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
// Immediately scalarize packed types containing only one element, so that
// the Legalize pass does not have to deal with them.
if (NumElements == 1) {
L = DAG.getLoad(PVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0)));
} else {
L = DAG.getVecLoad(NumElements, PVT, Root, Ptr,
DAG.getSrcValue(I.getOperand(0)));
}
} else {
L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr,
DAG.getSrcValue(I.getOperand(0)));

6
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -64,7 +64,7 @@ static void SetValueTypeAction(MVT::ValueType VT,
assert(VT < PromoteTo && "Must promote to a larger type!");
TransformToType[VT] = PromoteTo;
} else if (Action == TargetLowering::Expand) {
assert(MVT::isInteger(VT) && VT > MVT::i8 &&
assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
"Cannot expand this type: target must support SOME integer reg!");
// Expand to the next smaller integer type!
TransformToType[VT] = (MVT::ValueType)(VT-1);
@ -113,6 +113,10 @@ void TargetLowering::computeRegisterProperties() {
TransformToType, ValueTypeActions);
else
TransformToType[MVT::f32] = MVT::f32;
// Set MVT::Vector to always be Expanded
SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
ValueTypeActions);
assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
TransformToType[MVT::f64] = MVT::f64;