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Rather than attempting to legalize 1 x float, make sure the SD ISel never
generates it. Make MVT::Vector expand-only, and remove the code in Legalize that attempts to legalize it. The plan for supporting N x Type is to continually epxand it in ExpandOp until it gets down to 2 x Type, where it will be scalarized into a pair of scalars. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24482 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -925,26 +925,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
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return Result.getValue(Op.ResNo);
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case ISD::VLOAD:
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Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
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Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
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// If we just have one element, scalarize the result. Otherwise, check to
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// see if we support this operation on this type at this width. If not,
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// split the vector in half and try again.
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if (1 == cast<ConstantSDNode>(Node->getOperand(2))->getValue()) {
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MVT::ValueType SVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
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Result = LegalizeOp(DAG.getLoad(SVT, Tmp1, Tmp2, Node->getOperand(4)));
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} else {
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assert(0 && "Expand case for vectors unimplemented");
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}
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// Since loads produce two values, make sure to remember that we legalized
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// both of them.
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AddLegalizedOperand(SDOperand(Node, 0), Result);
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AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
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return Result.getValue(Op.ResNo);
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case ISD::EXTLOAD:
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case ISD::SEXTLOAD:
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case ISD::ZEXTLOAD: {
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@ -1685,28 +1665,6 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
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break;
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// Vector binary operators
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case ISD::VADD:
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case ISD::VSUB:
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case ISD::VMUL: {
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Tmp1 = Node->getOperand(0); // Element Count
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Tmp2 = Node->getOperand(1); // Element Type
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// If we just have one element, scalarize the result. Otherwise, check to
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// see if we support this operation on this type at this width. If not,
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// split the vector in half and try again.
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if (1 == cast<ConstantSDNode>(Tmp1)->getValue()) {
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MVT::ValueType SVT = cast<VTSDNode>(Tmp2)->getVT();
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Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), SVT), SVT,
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LegalizeOp(Node->getOperand(2)),
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LegalizeOp(Node->getOperand(3)));
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} else {
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assert(0 && "Expand case for vectors unimplemented");
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}
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break;
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}
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case ISD::BUILD_PAIR: {
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MVT::ValueType PairTy = Node->getValueType(0);
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// TODO: handle the case where the Lo and Hi operands are not of legal type
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@ -517,9 +517,19 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned IntOp, unsigned FPOp,
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setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
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} else {
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const PackedType *PTy = cast<PackedType>(Ty);
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SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
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SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
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setValue(&I, DAG.getNode(VecOp, Op1.getValueType(), Num, Typ, Op1, Op2));
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unsigned NumElements = PTy->getNumElements();
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MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
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// Immediately scalarize packed types containing only one element, so that
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// the Legalize pass does not have to deal with them.
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if (NumElements == 1) {
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unsigned Opc = MVT::isFloatingPoint(PVT) ? FPOp : IntOp;
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setValue(&I, DAG.getNode(Opc, PVT, Op1, Op2));
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} else {
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SDOperand Num = DAG.getConstant(NumElements, MVT::i32);
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SDOperand Typ = DAG.getValueType(PVT);
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setValue(&I, DAG.getNode(VecOp, Op1.getValueType(), Num, Typ, Op1, Op2));
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}
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}
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}
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@ -726,9 +736,17 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) {
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if (Type::PackedTyID == Ty->getTypeID()) {
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const PackedType *PTy = cast<PackedType>(Ty);
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L = DAG.getVecLoad(PTy->getNumElements(),
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TLI.getValueType(PTy->getElementType()), Root, Ptr,
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DAG.getSrcValue(I.getOperand(0)));
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unsigned NumElements = PTy->getNumElements();
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MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
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// Immediately scalarize packed types containing only one element, so that
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// the Legalize pass does not have to deal with them.
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if (NumElements == 1) {
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L = DAG.getLoad(PVT, Root, Ptr, DAG.getSrcValue(I.getOperand(0)));
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} else {
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L = DAG.getVecLoad(NumElements, PVT, Root, Ptr,
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DAG.getSrcValue(I.getOperand(0)));
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}
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} else {
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L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr,
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DAG.getSrcValue(I.getOperand(0)));
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@ -64,7 +64,7 @@ static void SetValueTypeAction(MVT::ValueType VT,
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assert(VT < PromoteTo && "Must promote to a larger type!");
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TransformToType[VT] = PromoteTo;
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} else if (Action == TargetLowering::Expand) {
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assert(MVT::isInteger(VT) && VT > MVT::i8 &&
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assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
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"Cannot expand this type: target must support SOME integer reg!");
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// Expand to the next smaller integer type!
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TransformToType[VT] = (MVT::ValueType)(VT-1);
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@ -113,6 +113,10 @@ void TargetLowering::computeRegisterProperties() {
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TransformToType, ValueTypeActions);
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else
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TransformToType[MVT::f32] = MVT::f32;
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// Set MVT::Vector to always be Expanded
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SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
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ValueTypeActions);
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assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
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TransformToType[MVT::f64] = MVT::f64;
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