mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Move most MMX instructions (defined as anything that
uses MMX, even if it also uses other things) from InstrSSE into InstrMMX. No (intended) functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113462 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
parent
bd6bf0848e
commit
4efb0feac8
@ -11,6 +11,9 @@
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// and properties of the instructions which are needed for code generation,
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// machine code emission, and analysis.
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//
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// All instructions that use MMX should be in this file, even if they also use
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// SSE.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -95,6 +98,56 @@ let Constraints = "$src1 = $dst" in {
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}
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}
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/// Unary MMX instructions requiring SSSE3.
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multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, Intrinsic IntId64> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
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}
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/// Binary MMX instructions requiring SSSE3.
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, Intrinsic IntId64> {
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let isCommutable = 0 in
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (mem_frag64 addr:$src2))))]>;
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}
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}
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/// PALIGN MMX instructions (require SSSE3).
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multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
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def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
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def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
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def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR64:$dst, (IntId VR64:$src1,
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(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
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}
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//===----------------------------------------------------------------------===//
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// MMX EMMS & FEMMS Instructions
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//===----------------------------------------------------------------------===//
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@ -192,7 +245,12 @@ def MMX_MOVZDI2PDIrm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst),
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(scalar_to_vector (loadi32 addr:$src))))))]>;
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// Arithmetic Instructions
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defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8,
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int_x86_ssse3_pabs_b>;
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defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16,
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int_x86_ssse3_pabs_w>;
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defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32,
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int_x86_ssse3_pabs_d>;
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// -- Addition
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defm MMX_PADDB : MMXI_binop_rm<0xFC, "paddb", add, v8i8, 1>,
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MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 1>;
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@ -208,6 +266,14 @@ defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 1>;
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defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 1>;
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defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
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defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16,
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int_x86_ssse3_phadd_w>;
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defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32,
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int_x86_ssse3_phadd_d>;
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defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16,
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int_x86_ssse3_phadd_sw>;
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// -- Subtraction
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defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>,
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MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b>;
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@ -224,6 +290,13 @@ defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
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defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b>;
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defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w>;
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defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16,
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int_x86_ssse3_phsub_w>;
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defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32,
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int_x86_ssse3_phsub_d>;
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defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16,
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int_x86_ssse3_phsub_sw>;
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// -- Multiplication
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defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>,
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MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 1>;
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@ -231,10 +304,15 @@ defm MMX_PMULLW : MMXI_binop_rm<0xD5, "pmullw", mul, v4i16, 1>,
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defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 1>;
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defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 1>;
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defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 1>;
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let isCommutable = 1 in
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defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16,
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int_x86_ssse3_pmul_hr_sw>;
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// -- Miscellanea
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defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 1>;
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defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8,
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int_x86_ssse3_pmadd_ub_sw>;
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defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 1>;
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defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 1>;
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@ -246,6 +324,35 @@ defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 1>;
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defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 1>;
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defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8,
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int_x86_ssse3_psign_b>;
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defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16,
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int_x86_ssse3_psign_w>;
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defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32,
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int_x86_ssse3_psign_d>;
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let Constraints = "$src1 = $dst" in
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defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
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let AddedComplexity = 5 in {
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def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1,
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(SHUFFLE_get_palign_imm VR64:$src3))>,
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Requires<[HasSSSE3]>;
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}
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// Logical Instructions
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defm MMX_PAND : MMXI_binop_rm_v1i64<0xDB, "pand", and, 1>,
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MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 1>;
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@ -412,6 +519,18 @@ def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(mmx_pshufw:$src2 (bc_v4i16 (load_mmx addr:$src1)),
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(undef)))]>;
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defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8,
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int_x86_ssse3_pshuf_b>;
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// Shuffle with PALIGN
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def : Pat<(v1i64 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
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def : Pat<(v2i32 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
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def : Pat<(v4i16 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
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def : Pat<(v8i8 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
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(MMX_PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
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// -- Conversion Instructions
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let neverHasSideEffects = 1 in {
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def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
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@ -3532,18 +3532,6 @@ let Constraints = "$src1 = $dst" in {
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// SSSE3 - Packed Absolute Instructions
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//===---------------------------------------------------------------------===//
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/// SS3I_unop_rm_int_mm - Simple SSSE3 unary whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, Intrinsic IntId64> {
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst, (IntId64 VR64:$src))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR64:$dst,
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(IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
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}
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/// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
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multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
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@ -3572,19 +3560,11 @@ let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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}
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defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
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int_x86_ssse3_pabs_b_128>,
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SS3I_unop_rm_int_mm<0x1C, "pabsb", memopv8i8,
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int_x86_ssse3_pabs_b>;
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int_x86_ssse3_pabs_b_128>;
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defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
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int_x86_ssse3_pabs_w_128>,
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SS3I_unop_rm_int_mm<0x1D, "pabsw", memopv4i16,
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int_x86_ssse3_pabs_w>;
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int_x86_ssse3_pabs_w_128>;
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defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
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int_x86_ssse3_pabs_d_128>,
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SS3I_unop_rm_int_mm<0x1E, "pabsd", memopv2i32,
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int_x86_ssse3_pabs_d>;
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int_x86_ssse3_pabs_d_128>;
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//===---------------------------------------------------------------------===//
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// SSSE3 - Packed Binary Operator Instructions
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@ -3611,20 +3591,6 @@ multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
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PatFrag mem_frag64, Intrinsic IntId64> {
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let isCommutable = 1 in
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def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
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(ins VR64:$src1, VR64:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
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def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
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(ins VR64:$src1, i64mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR64:$dst,
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(IntId64 VR64:$src1,
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(bitconvert (memopv8i8 addr:$src2))))]>;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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let isCommutable = 0 in {
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@ -3659,54 +3625,30 @@ defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
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let ImmT = NoImm, Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
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int_x86_ssse3_phadd_w_128>,
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SS3I_binop_rm_int_mm<0x01, "phaddw", memopv4i16,
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int_x86_ssse3_phadd_w>;
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int_x86_ssse3_phadd_w_128>;
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defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
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int_x86_ssse3_phadd_d_128>,
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SS3I_binop_rm_int_mm<0x02, "phaddd", memopv2i32,
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int_x86_ssse3_phadd_d>;
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int_x86_ssse3_phadd_d_128>;
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defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
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int_x86_ssse3_phadd_sw_128>,
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SS3I_binop_rm_int_mm<0x03, "phaddsw", memopv4i16,
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int_x86_ssse3_phadd_sw>;
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int_x86_ssse3_phadd_sw_128>;
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defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
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int_x86_ssse3_phsub_w_128>,
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SS3I_binop_rm_int_mm<0x05, "phsubw", memopv4i16,
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int_x86_ssse3_phsub_w>;
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int_x86_ssse3_phsub_w_128>;
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defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
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int_x86_ssse3_phsub_d_128>,
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SS3I_binop_rm_int_mm<0x06, "phsubd", memopv2i32,
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int_x86_ssse3_phsub_d>;
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int_x86_ssse3_phsub_d_128>;
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defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
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int_x86_ssse3_phsub_sw_128>,
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SS3I_binop_rm_int_mm<0x07, "phsubsw", memopv4i16,
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int_x86_ssse3_phsub_sw>;
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int_x86_ssse3_phsub_sw_128>;
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defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
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int_x86_ssse3_pmadd_ub_sw_128>,
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SS3I_binop_rm_int_mm<0x04, "pmaddubsw", memopv8i8,
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int_x86_ssse3_pmadd_ub_sw>;
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int_x86_ssse3_pmadd_ub_sw_128>;
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defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8,
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int_x86_ssse3_pshuf_b_128>,
|
||||
SS3I_binop_rm_int_mm<0x00, "pshufb", memopv8i8,
|
||||
int_x86_ssse3_pshuf_b>;
|
||||
int_x86_ssse3_pshuf_b_128>;
|
||||
defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
|
||||
int_x86_ssse3_psign_b_128>,
|
||||
SS3I_binop_rm_int_mm<0x08, "psignb", memopv8i8,
|
||||
int_x86_ssse3_psign_b>;
|
||||
int_x86_ssse3_psign_b_128>;
|
||||
defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
|
||||
int_x86_ssse3_psign_w_128>,
|
||||
SS3I_binop_rm_int_mm<0x09, "psignw", memopv4i16,
|
||||
int_x86_ssse3_psign_w>;
|
||||
int_x86_ssse3_psign_w_128>;
|
||||
defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
|
||||
int_x86_ssse3_psign_d_128>,
|
||||
SS3I_binop_rm_int_mm<0x0A, "psignd", memopv2i32,
|
||||
int_x86_ssse3_psign_d>;
|
||||
int_x86_ssse3_psign_d_128>;
|
||||
}
|
||||
defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
|
||||
int_x86_ssse3_pmul_hr_sw_128>,
|
||||
SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", memopv4i16,
|
||||
int_x86_ssse3_pmul_hr_sw>;
|
||||
int_x86_ssse3_pmul_hr_sw_128>;
|
||||
}
|
||||
|
||||
def : Pat<(X86pshufb VR128:$src, VR128:$mask),
|
||||
@ -3718,24 +3660,6 @@ def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
|
||||
// SSSE3 - Packed Align Instruction Patterns
|
||||
//===---------------------------------------------------------------------===//
|
||||
|
||||
multiclass ssse3_palign_mm<string asm, Intrinsic IntId> {
|
||||
def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
|
||||
(ins VR64:$src1, VR64:$src2, i8imm:$src3),
|
||||
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
|
||||
def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
|
||||
(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
|
||||
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
|
||||
def R64irr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
|
||||
(ins VR64:$src1, VR64:$src2, i8imm:$src3),
|
||||
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>;
|
||||
def R64irm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
|
||||
(ins VR64:$src1, i64mem:$src2, i8imm:$src3),
|
||||
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
|
||||
[(set VR64:$dst, (IntId VR64:$src1,
|
||||
(bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>;
|
||||
}
|
||||
|
||||
multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
|
||||
def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2, i8imm:$src3),
|
||||
@ -3756,28 +3680,9 @@ multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
|
||||
let isAsmParserOnly = 1, Predicates = [HasAVX] in
|
||||
defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
|
||||
let Constraints = "$src1 = $dst" in
|
||||
defm PALIGN : ssse3_palign<"palignr">,
|
||||
ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>;
|
||||
defm PALIGN : ssse3_palign<"palignr">;
|
||||
|
||||
let AddedComplexity = 5 in {
|
||||
|
||||
def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
||||
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
||||
Requires<[HasSSSE3]>;
|
||||
def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
||||
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
||||
Requires<[HasSSSE3]>;
|
||||
def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
||||
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
||||
Requires<[HasSSSE3]>;
|
||||
def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1,
|
||||
(SHUFFLE_get_palign_imm VR64:$src3))>,
|
||||
Requires<[HasSSSE3]>;
|
||||
|
||||
def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
|
||||
(PALIGNR128rr VR128:$src2, VR128:$src1,
|
||||
(SHUFFLE_get_palign_imm VR128:$src3))>,
|
||||
@ -5907,15 +5812,6 @@ def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
|
||||
(PSHUFLWmi addr:$src, imm:$imm)>;
|
||||
|
||||
// Shuffle with PALIGN
|
||||
def : Pat<(v1i64 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
|
||||
def : Pat<(v2i32 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
|
||||
def : Pat<(v4i16 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
|
||||
def : Pat<(v8i8 (X86PAlign VR64:$src1, VR64:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR64rr VR64:$src2, VR64:$src1, imm:$imm)>;
|
||||
|
||||
def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
(PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
|
||||
def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user