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fix some spell mistakes around 'ConcatVector' and 'ShuffleVector' in AArch64 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199858 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4154,8 +4154,8 @@ AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
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return false;
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}
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// Check whether a shuffle_vecotor could be presented as conact_vector.
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bool AArch64TargetLowering::isConactVector(SDValue Op,SelectionDAG &DAG,
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// Check whether a shuffle_vector could be presented as concat_vector.
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bool AArch64TargetLowering::isConcatVector(SDValue Op,SelectionDAG &DAG,
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SDValue V0, SDValue V1,
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const int* Mask,
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SDValue &Res) const {
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@ -4465,7 +4465,7 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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return LowerVECTOR_SHUFFLE(Shuffle, DAG);
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} else {
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SDValue Res;
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if(isConactVector(Op, DAG, V0, V1, Mask, Res))
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if(isConcatVector(Op, DAG, V0, V1, Mask, Res))
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return Res;
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}
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}
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@ -4655,7 +4655,7 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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}
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SDValue Res;
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if (isConactVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
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if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
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return Res;
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// If the element of shuffle mask are all the same constant, we can
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@ -232,7 +232,7 @@ public:
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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bool isConactVector(SDValue Op,SelectionDAG &DAG, SDValue V0, SDValue V1,
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bool isConcatVector(SDValue Op,SelectionDAG &DAG, SDValue V0, SDValue V1,
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const int* Mask, SDValue &Res) const;
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bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &V0,
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