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Mess around with allocation order. In particular, I think we ought to be
using the local & in regs first because they are not clobbered by calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14228 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -69,10 +69,10 @@ let Namespace = "V8" in {
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// FIXME: the register order should be defined in terms of the preferred
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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// allocation order...
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//
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//
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def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
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def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
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O0, O1, O2, O3, O4, O5, O7,
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L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5,
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I0, I1, I2, I3, I4, I5,
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G1, G2, G3, G4, G5, G6, G7,
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O0, O1, O2, O3, O4, O5, O7,
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// Non-allocatable regs
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// Non-allocatable regs
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O6, I6, I7, G0]> {
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O6, I6, I7, G0]> {
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let Methods = [{
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let Methods = [{
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@@ -69,10 +69,10 @@ let Namespace = "V8" in {
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// FIXME: the register order should be defined in terms of the preferred
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// FIXME: the register order should be defined in terms of the preferred
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// allocation order...
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// allocation order...
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//
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//
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def IntRegs : RegisterClass<i32, 8, [G1, G2, G3, G4, G5, G6, G7,
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def IntRegs : RegisterClass<i32, 8, [L0, L1, L2, L3, L4, L5, L6, L7,
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O0, O1, O2, O3, O4, O5, O7,
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L0, L1, L2, L3, L4, L5, L6, L7,
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I0, I1, I2, I3, I4, I5,
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I0, I1, I2, I3, I4, I5,
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G1, G2, G3, G4, G5, G6, G7,
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O0, O1, O2, O3, O4, O5, O7,
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// Non-allocatable regs
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// Non-allocatable regs
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O6, I6, I7, G0]> {
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O6, I6, I7, G0]> {
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let Methods = [{
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let Methods = [{
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