6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 20:32:21 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Fix READLANE and WRITELANE lane select for VI

Browse Source 
VOP2 declares vsrc1, but VOP3 declares src1.
We can't use the same "ins" if the operands have different names in VOP2
and VOP3 encodings.

This fixes a hang in geometry shaders which spill M0 on VI.
(BTW it doesn't look like M0 needs spilling and the spilling seems
duplicated 3 times)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229752 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Marek Olsak 2015-02-18 22:12:45 +00:00
parent 2a0d0dedf0
commit 4f5a891372
2 changed files with 6 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
lib/Target/R600/SIInstrFormats.td
View File

@ -289,10 +289,10 @@ class VOP1e <bits<8> op> : Enc32 {
class VOP2e <bits<6> op> : Enc32 { class VOP2e <bits<6> op> : Enc32 {
bits<8> vdst; bits<8> vdst;
bits<9> src0; bits<9> src0;
bits<8> vsrc1; bits<8> src1;
let Inst{8-0} = src0; let Inst{8-0} = src0;
let Inst{16-9} = vsrc1; let Inst{16-9} = src1;
let Inst{24-17} = vdst; let Inst{24-17} = vdst;
let Inst{30-25} = op; let Inst{30-25} = op;
let Inst{31} = 0x0; //encoding let Inst{31} = 0x0; //encoding

8
lib/Target/R600/SIInstructions.td
View File

@ -1533,16 +1533,16 @@ defm V_READLANE_B32 : VOP2SI_3VI_m <
vop3 <0x001, 0x289>, vop3 <0x001, 0x289>,
"v_readlane_b32", "v_readlane_b32",
(outs SReg_32:$vdst), (outs SReg_32:$vdst),
(ins VGPR_32:$src0, SSrc_32:$vsrc1), (ins VGPR_32:$src0, SCSrc_32:$src1),
"v_readlane_b32 $vdst, $src0, $vsrc1" "v_readlane_b32 $vdst, $src0, $src1"
>; >;
defm V_WRITELANE_B32 : VOP2SI_3VI_m < defm V_WRITELANE_B32 : VOP2SI_3VI_m <
vop3 <0x002, 0x28a>, vop3 <0x002, 0x28a>,
"v_writelane_b32", "v_writelane_b32",
(outs VGPR_32:$vdst), (outs VGPR_32:$vdst),
(ins SReg_32:$src0, SSrc_32:$vsrc1), (ins SReg_32:$src0, SCSrc_32:$src1),
"v_writelane_b32 $vdst, $src0, $vsrc1" "v_writelane_b32 $vdst, $src0, $src1"
>; >;
// These instructions only exist on SI and CI // These instructions only exist on SI and CI