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This corrects creation of operands for t2PLDW. It also removes the definition of t2PLDWpci,

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as pldw does not have a literal variant (i.e. pc relative version)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187804 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mihai Popa 2013-08-06 16:07:46 +00:00
parent 4a378b95aa
commit 4f7092176c
4 changed files with 34 additions and 30 deletions
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29
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -1604,19 +1604,21 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let DecoderMethod = "DecodeT2LoadShift";
}
}
defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
// pci variant is very similar to i12, but supports negative offsets
// from the PC.
def pci : T2Iso<(outs), (ins t2ldrlabel:$addr), IIC_Preload, opc,
"\t$addr",
// from the PC. Only PLD and PLI have pci variants (not PLDW)
class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
IIC_Preload, opc, "\t$addr",
[(ARMPreload (ARMWrapper tconstpool:$addr),
(i32 write), (i32 instr))]>,
Sched<[WritePreLd]> {
(i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
let Inst{31-25} = 0b1111100;
let Inst{24} = instr;
let Inst{22} = 0;
let Inst{21} = write;
let Inst{20} = 1;
let Inst{24} = inst;
let Inst{22-20} = 0b001;
let Inst{19-16} = 0b1111;
let Inst{15-12} = 0b1111;
@ -1626,11 +1628,9 @@ multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> {
let DecoderMethod = "DecodeT2LoadLabel";
}
}
defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>;
defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>;
defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
def t2PLDpci : T2Iplpci<0, "pld">, Requires<[IsThumb2]>;
def t2PLIpci : T2Iplpci<1, "pli">, Requires<[IsThumb2,HasV7]>;
//===----------------------------------------------------------------------===//
// Load / store multiple Instructions.
@ -4425,9 +4425,6 @@ def : t2InstAlias<"add${p} $Rd, pc, $imm",
// PLD/PLDW/PLI with alternate literal form.
def : t2InstAlias<"pld${p} $addr",
(t2PLDpci t2ldr_pcrel_imm12:$addr, pred:$p)>;
def : InstAlias<"pldw${p} $addr",
(t2PLDWpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
Requires<[IsThumb2,HasV7,HasMP]>;
def : InstAlias<"pli${p} $addr",
(t2PLIpci t2ldr_pcrel_imm12:$addr, pred:$p)>,
Requires<[IsThumb2,HasV7]>;

2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -3354,6 +3354,7 @@ static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
switch (Inst.getOpcode()) {
case ARM::t2PLDi8:
case ARM::t2PLIi8:
case ARM::t2PLDWi8:
break;
default:
if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
@ -3417,6 +3418,7 @@ static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
switch (Inst.getOpcode()) {
case ARM::t2PLDi12:
case ARM::t2PLDWi12:
case ARM::t2PLIi12:
break;
default:

5
test/MC/ARM/thumb-diagnostics.s
View File

@ -156,3 +156,8 @@ error: invalid operand for instruction
@ CHECK-ERRORS: yield
@ CHECK-ERRORS: ^
@------------------------------------------------------------------------------
@ PLDW required mp-extensions
@------------------------------------------------------------------------------
pldw [r0, #4]
@ CHECK-ERRORS: error: instruction requires: mp-extensions

4
test/MC/ARM/thumb2-pldw.s
View File

@ -3,5 +3,5 @@
@------------------------------------------------------------------------------
@ PLD(literal)
@------------------------------------------------------------------------------
pldw [pc,#-4095]
@ CHECK: pldw [pc, #-4095] @ encoding: [0x3f,0xf8,0xff,0xff]
pldw [r0, #257]
@ CHECK: pldw [r0, #257] @ encoding: [0xb0,0xf8,0x01,0xf1]