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Add SARX/SHRX/SHLX code generation support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao
parent
6bcdb5b903
commit
4fa2ddbb94
@ -565,6 +565,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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// BMI/BMI2 foldable instructions
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{ X86::RORX32ri, X86::RORX32mi, 0 },
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{ X86::RORX64ri, X86::RORX64mi, 0 },
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{ X86::SARX32rr, X86::SARX32rm, 0 },
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{ X86::SARX64rr, X86::SARX64rm, 0 },
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{ X86::SHRX32rr, X86::SHRX32rm, 0 },
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{ X86::SHRX64rr, X86::SHRX64rm, 0 },
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{ X86::SHLX32rr, X86::SHLX32rm, 0 },
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{ X86::SHLX64rr, X86::SHLX64rm, 0 },
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
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@ -896,4 +896,59 @@ let Predicates = [HasBMI2] in {
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(RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
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def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
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(RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
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// Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
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// immedidate shift, i.e. the following code is considered better
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//
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// mov %edi, %esi
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// shl $imm, %esi
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// ... %edi, ...
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//
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// than
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//
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// movb $imm, %sil
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// shlx %sil, %edi, %esi
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// ... %edi, ...
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//
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let AddedComplexity = 1 in {
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def : Pat<(sra GR32:$src1, GR8:$src2),
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(SARX32rr GR32:$src1,
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(INSERT_SUBREG
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(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(sra GR64:$src1, GR8:$src2),
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(SARX64rr GR64:$src1,
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(INSERT_SUBREG
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(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(srl GR32:$src1, GR8:$src2),
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(SHRX32rr GR32:$src1,
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(INSERT_SUBREG
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(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(srl GR64:$src1, GR8:$src2),
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(SHRX64rr GR64:$src1,
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(INSERT_SUBREG
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(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(shl GR32:$src1, GR8:$src2),
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(SHLX32rr GR32:$src1,
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(INSERT_SUBREG
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(i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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def : Pat<(shl GR64:$src1, GR8:$src2),
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(SHLX64rr GR64:$src1,
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(INSERT_SUBREG
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(i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
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}
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// Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor
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//
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// mov (%ecx), %esi
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// shl $imm, $esi
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//
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// over
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//
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// movb $imm %al
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// shlx %al, (%ecx), %esi
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//
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// As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
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// optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
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; rdar://5571034
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; This requires physreg joining, %vreg13 is live everywhere:
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178
test/CodeGen/X86/shift-bmi2.ll
Normal file
178
test/CodeGen/X86/shift-bmi2.ll
Normal file
@ -0,0 +1,178 @@
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; RUN: llc -mtriple=i386-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI2 %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 < %s | FileCheck --check-prefix=BMI264 %s
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define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
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entry:
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%shl = shl i32 %x, %shamt
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; BMI2: shl32
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; BMI2: shlxl
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; BMI2: ret
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; BMI264: shl32
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; BMI264: shlxl
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; BMI264: ret
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ret i32 %shl
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}
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define i32 @shl32i(i32 %x) nounwind uwtable readnone {
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entry:
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%shl = shl i32 %x, 5
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; BMI2: shl32i
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; BMI2-NOT: shlxl
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; BMI2: ret
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; BMI264: shl32i
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; BMI264-NOT: shlxl
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; BMI264: ret
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ret i32 %shl
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}
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define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
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entry:
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%x = load i32* %p
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%shl = shl i32 %x, %shamt
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; BMI2: shl32p
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; BMI2: shlxl %{{.+}}, ({{.+}}), %{{.+}}
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; BMI2: ret
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; BMI264: shl32p
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; BMI264: shlxl %{{.+}}, ({{.+}}), %{{.+}}
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; BMI264: ret
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ret i32 %shl
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}
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define i32 @shl32pi(i32* %p) nounwind uwtable readnone {
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entry:
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%x = load i32* %p
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%shl = shl i32 %x, 5
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; BMI2: shl32pi
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; BMI2-NOT: shlxl
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; BMI2: ret
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; BMI264: shl32pi
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; BMI264-NOT: shlxl
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; BMI264: ret
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ret i32 %shl
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}
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define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
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entry:
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%shl = shl i64 %x, %shamt
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; BMI264: shl64
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; BMI264: shlxq
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; BMI264: ret
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ret i64 %shl
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}
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define i64 @shl64i(i64 %x) nounwind uwtable readnone {
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entry:
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%shl = shl i64 %x, 7
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; BMI264: shl64i
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; BMI264-NOT: shlxq
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; BMI264: ret
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ret i64 %shl
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}
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define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
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entry:
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%x = load i64* %p
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%shl = shl i64 %x, %shamt
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; BMI264: shl64p
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; BMI264: shlxq %{{.+}}, ({{.+}}), %{{.+}}
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; BMI264: ret
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ret i64 %shl
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}
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define i64 @shl64pi(i64* %p) nounwind uwtable readnone {
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entry:
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%x = load i64* %p
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%shl = shl i64 %x, 7
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; BMI264: shl64p
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; BMI264-NOT: shlxq
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; BMI264: ret
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ret i64 %shl
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}
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define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
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entry:
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%shl = lshr i32 %x, %shamt
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; BMI2: lshr32
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; BMI2: shrxl
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; BMI2: ret
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; BMI264: lshr32
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; BMI264: shrxl
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; BMI264: ret
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ret i32 %shl
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}
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define i32 @lshr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
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entry:
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%x = load i32* %p
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%shl = lshr i32 %x, %shamt
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; BMI2: lshr32p
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; BMI2: shrxl %{{.+}}, ({{.+}}), %{{.+}}
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; BMI2: ret
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; BMI264: lshr32
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; BMI264: shrxl %{{.+}}, ({{.+}}), %{{.+}}
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; BMI264: ret
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ret i32 %shl
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}
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define i64 @lshr64(i64 %x, i64 %shamt) nounwind uwtable readnone {
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entry:
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%shl = lshr i64 %x, %shamt
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; BMI264: lshr64
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; BMI264: shrxq
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; BMI264: ret
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ret i64 %shl
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}
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define i64 @lshr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
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entry:
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%x = load i64* %p
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%shl = lshr i64 %x, %shamt
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; BMI264: lshr64p
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; BMI264: shrxq %{{.+}}, ({{.+}}), %{{.+}}
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; BMI264: ret
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ret i64 %shl
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}
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define i32 @ashr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
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entry:
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%shl = ashr i32 %x, %shamt
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; BMI2: ashr32
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; BMI2: sarxl
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; BMI2: ret
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; BMI264: ashr32
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; BMI264: sarxl
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; BMI264: ret
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ret i32 %shl
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}
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define i32 @ashr32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
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entry:
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%x = load i32* %p
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%shl = ashr i32 %x, %shamt
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; BMI2: ashr32p
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; BMI2: sarxl %{{.+}}, ({{.+}}), %{{.+}}
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; BMI2: ret
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; BMI264: ashr32
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; BMI264: sarxl %{{.+}}, ({{.+}}), %{{.+}}
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; BMI264: ret
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ret i32 %shl
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}
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define i64 @ashr64(i64 %x, i64 %shamt) nounwind uwtable readnone {
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entry:
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%shl = ashr i64 %x, %shamt
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; BMI264: ashr64
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; BMI264: sarxq
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; BMI264: ret
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ret i64 %shl
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}
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define i64 @ashr64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
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entry:
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%x = load i64* %p
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%shl = ashr i64 %x, %shamt
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; BMI264: ashr64p
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; BMI264: sarxq %{{.+}}, ({{.+}}), %{{.+}}
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; BMI264: ret
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ret i64 %shl
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}
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=i386-apple-darwin9 -fast-isel=false -O0 < %s | FileCheck %s
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; RUN: llc -mtriple=i386-apple-darwin9 -mcpu=corei7 -fast-isel=false -O0 < %s | FileCheck %s
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; Gather non-machine specific tests for the transformations in
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; CodeGen/SelectionDAG/TargetLowering. Currently, these
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