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[mips][msa] Fix issue with immediate fields of LD/ST instructions
not being correctly encoded/decoded. In more detail, immediate fields of LD/ST instructions should be divided/multiplied by the size of the data format before encoding and after decoding, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196494 91177308-0d34-0410-b5e6-96231b3b80d8
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52123d1842
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@ -565,7 +565,37 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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Inst.addOperand(MCOperand::CreateReg(Reg));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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// The immediate field of an LD/ST instruction is scaled which means it must
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// be multiplied (when decoding) by the size (in bytes) of the instructions'
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// data format.
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// .b - 1 byte
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// .h - 2 bytes
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// .w - 4 bytes
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// .d - 8 bytes
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switch(Inst.getOpcode())
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{
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default:
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assert (0 && "Unexpected instruction");
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return MCDisassembler::Fail;
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break;
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case Mips::LD_B:
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case Mips::ST_B:
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Inst.addOperand(MCOperand::CreateImm(Offset));
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break;
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case Mips::LD_H:
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case Mips::ST_H:
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Inst.addOperand(MCOperand::CreateImm(Offset << 1));
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break;
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case Mips::LD_W:
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case Mips::ST_W:
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Inst.addOperand(MCOperand::CreateImm(Offset << 2));
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break;
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case Mips::LD_D:
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case Mips::ST_D:
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Inst.addOperand(MCOperand::CreateImm(Offset << 3));
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break;
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}
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return MCDisassembler::Success;
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}
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@ -107,6 +107,9 @@ public:
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unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo,
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@ -480,6 +483,49 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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return getExprOpValue(MO.getExpr(),Fixups);
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}
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/// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST
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/// instructions.
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unsigned
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MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Base register is encoded in bits 20-16, offset is encoded in bits 15-0.
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assert(MI.getOperand(OpNo).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16;
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unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups);
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// The immediate field of an LD/ST instruction is scaled which means it must
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// be divided (when encoding) by the size (in bytes) of the instructions'
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// data format.
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// .b - 1 byte
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// .h - 2 bytes
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// .w - 4 bytes
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// .d - 8 bytes
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switch(MI.getOpcode())
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{
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default:
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assert (0 && "Unexpected instruction");
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break;
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case Mips::LD_B:
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case Mips::ST_B:
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// We don't need to scale the offset in this case
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break;
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case Mips::LD_H:
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case Mips::ST_H:
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OffBits >>= 1;
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break;
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case Mips::LD_W:
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case Mips::ST_W:
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OffBits >>= 2;
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break;
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case Mips::LD_D:
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case Mips::ST_D:
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OffBits >>= 3;
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break;
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}
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return (OffBits & 0xFFFF) | RegBits;
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}
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/// getMemEncoding - Return binary encoding of memory related operand.
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/// If the offset operand requires relocation, record the relocation.
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unsigned
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@ -112,6 +112,7 @@ private:
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unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const;
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@ -224,6 +225,12 @@ unsigned MipsCodeEmitter::getMemEncodingMMImm12(const MachineInstr &MI,
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return 0;
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}
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unsigned MipsCodeEmitter::getMSAMemEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("Unimplemented function.");
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return 0;
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}
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unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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// size is encoded as size-1.
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@ -302,8 +302,7 @@ def InvertedImOperand : Operand<i32> {
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let ParserMatchClass = MipsInvertedImmoperand;
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}
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// Address operand
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def mem : Operand<iPTR> {
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class mem_generic : Operand<iPTR> {
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let PrintMethod = "printMemOperand";
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let MIOperandInfo = (ops ptr_rc, simm16);
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let EncoderMethod = "getMemEncoding";
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@ -311,6 +310,14 @@ def mem : Operand<iPTR> {
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let OperandType = "OPERAND_MEMORY";
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}
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// Address operand
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def mem : mem_generic;
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// MSA specific address operand
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def mem_msa : mem_generic {
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let EncoderMethod = "getMSAMemEncoding";
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}
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def mem_ea : Operand<iPTR> {
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let PrintMethod = "printMemOperandEA";
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let MIOperandInfo = (ops ptr_rc, simm16);
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@ -2269,7 +2269,7 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
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class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, RegisterOperand ROWD,
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Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
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Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs ROWD:$wd);
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dag InOperandList = (ins MemOpnd:$addr);
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@ -2590,7 +2590,7 @@ class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
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class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
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ValueType TyNode, RegisterOperand ROWD,
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Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
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Operand MemOpnd = mem_msa, ComplexPattern Addr = addrRegImm,
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InstrItinClass itin = NoItinerary> {
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dag OutOperandList = (outs);
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dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
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@ -2,29 +2,83 @@
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#
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# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
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#
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# CHECK: ld.b $w2, 1($7) # encoding: [0x78,0x01,0x38,0xa0]
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# CHECK: ld.h $w16, -9($zero) # encoding: [0x7b,0xf7,0x04,0x21]
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# CHECK: ld.w $w13, -6($4) # encoding: [0x7b,0xfa,0x23,0x62]
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# CHECK: ld.d $w1, -5($16) # encoding: [0x7b,0xfb,0x80,0x63]
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# CHECK: st.b $w29, 1($14) # encoding: [0x78,0x01,0x77,0x64]
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# CHECK: st.h $w6, -1($8) # encoding: [0x7b,0xff,0x41,0xa5]
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# CHECK: st.w $w18, 8($15) # encoding: [0x78,0x08,0x7c,0xa6]
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# CHECK: st.d $w3, -14($18) # encoding: [0x7b,0xf2,0x90,0xe7]
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# CHECK: ld.b $w0, -512($1) # encoding: [0x7a,0x00,0x08,0x20]
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# CHECK: ld.b $w1, 0($2) # encoding: [0x78,0x00,0x10,0x60]
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# CHECK: ld.b $w2, 511($3) # encoding: [0x79,0xff,0x18,0xa0]
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# CHECKOBJDUMP: ld.b $w2, 1($7)
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# CHECKOBJDUMP: ld.h $w16, -9($zero)
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# CHECKOBJDUMP: ld.w $w13, -6($4)
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# CHECKOBJDUMP: ld.d $w1, -5($16)
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# CHECKOBJDUMP: st.b $w29, 1($14)
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# CHECKOBJDUMP: st.h $w6, -1($8)
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# CHECKOBJDUMP: st.w $w18, 8($15)
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# CHECKOBJDUMP: st.d $w3, -14($18)
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# CHECK: ld.h $w3, -1024($4) # encoding: [0x7a,0x00,0x20,0xe1]
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# CHECK: ld.h $w4, -512($5) # encoding: [0x7b,0x00,0x29,0x21]
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# CHECK: ld.h $w5, 0($6) # encoding: [0x78,0x00,0x31,0x61]
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# CHECK: ld.h $w6, 512($7) # encoding: [0x79,0x00,0x39,0xa1]
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# CHECK: ld.h $w7, 1022($8) # encoding: [0x79,0xff,0x41,0xe1]
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ld.b $w2, 1($7)
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ld.h $w16, -9($zero)
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ld.w $w13, -6($4)
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ld.d $w1, -5($16)
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st.b $w29, 1($14)
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st.h $w6, -1($8)
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st.w $w18, 8($15)
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st.d $w3, -14($18)
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# CHECK: ld.w $w8, -2048($9) # encoding: [0x7a,0x00,0x4a,0x22]
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# CHECK: ld.w $w9, -1024($10) # encoding: [0x7b,0x00,0x52,0x62]
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# CHECK: ld.w $w10, -512($11) # encoding: [0x7b,0x80,0x5a,0xa2]
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# CHECK: ld.w $w11, 512($12) # encoding: [0x78,0x80,0x62,0xe2]
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# CHECK: ld.w $w12, 1024($13) # encoding: [0x79,0x00,0x6b,0x22]
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# CHECK: ld.w $w13, 2044($14) # encoding: [0x79,0xff,0x73,0x62]
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# CHECK: ld.d $w14, -4096($15) # encoding: [0x7a,0x00,0x7b,0xa3]
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# CHECK: ld.d $w15, -2048($16) # encoding: [0x7b,0x00,0x83,0xe3]
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# CHECK: ld.d $w16, -1024($17) # encoding: [0x7b,0x80,0x8c,0x23]
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# CHECK: ld.d $w17, -512($18) # encoding: [0x7b,0xc0,0x94,0x63]
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# CHECK: ld.d $w18, 0($19) # encoding: [0x78,0x00,0x9c,0xa3]
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# CHECK: ld.d $w19, 512($20) # encoding: [0x78,0x40,0xa4,0xe3]
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# CHECK: ld.d $w20, 1024($21) # encoding: [0x78,0x80,0xad,0x23]
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# CHECK: ld.d $w21, 2048($22) # encoding: [0x79,0x00,0xb5,0x63]
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# CHECK: ld.d $w22, 4088($23) # encoding: [0x79,0xff,0xbd,0xa3]
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# CHECKOBJDUMP: ld.b $w0, -512($1)
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# CHECKOBJDUMP: ld.b $w1, 0($2)
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# CHECKOBJDUMP: ld.b $w2, 511($3)
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# CHECKOBJDUMP: ld.h $w3, -1024($4)
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# CHECKOBJDUMP: ld.h $w4, -512($5)
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# CHECKOBJDUMP: ld.h $w5, 0($6)
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# CHECKOBJDUMP: ld.h $w6, 512($7)
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# CHECKOBJDUMP: ld.h $w7, 1022($8)
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# CHECKOBJDUMP: ld.w $w8, -2048($9)
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# CHECKOBJDUMP: ld.w $w9, -1024($10)
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# CHECKOBJDUMP: ld.w $w10, -512($11)
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# CHECKOBJDUMP: ld.w $w11, 512($12)
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# CHECKOBJDUMP: ld.w $w12, 1024($13)
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# CHECKOBJDUMP: ld.w $w13, 2044($14)
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# CHECKOBJDUMP: ld.d $w14, -4096($15)
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# CHECKOBJDUMP: ld.d $w15, -2048($16)
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# CHECKOBJDUMP: ld.d $w16, -1024($17)
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# CHECKOBJDUMP: ld.d $w17, -512($18)
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# CHECKOBJDUMP: ld.d $w18, 0($19)
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# CHECKOBJDUMP: ld.d $w19, 512($20)
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# CHECKOBJDUMP: ld.d $w20, 1024($21)
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# CHECKOBJDUMP: ld.d $w21, 2048($22)
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# CHECKOBJDUMP: ld.d $w22, 4088($23)
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ld.b $w0, -512($1)
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ld.b $w1, 0($2)
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ld.b $w2, 511($3)
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ld.h $w3, -1024($4)
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ld.h $w4, -512($5)
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ld.h $w5, 0($6)
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ld.h $w6, 512($7)
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ld.h $w7, 1022($8)
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ld.w $w8, -2048($9)
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ld.w $w9, -1024($10)
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ld.w $w10, -512($11)
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ld.w $w11, 512($12)
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ld.w $w12, 1024($13)
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ld.w $w13, 2044($14)
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ld.d $w14, -4096($15)
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ld.d $w15, -2048($16)
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ld.d $w16, -1024($17)
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ld.d $w17, -512($18)
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ld.d $w18, 0($19)
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ld.d $w19, 512($20)
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ld.d $w20, 1024($21)
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ld.d $w21, 2048($22)
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ld.d $w22, 4088($23)
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