diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp index af1607e2a3b..b9a61ef3e44 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp @@ -39,72 +39,92 @@ public: ~AArch64MCCodeEmitter() {} unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; template unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { - return getOffsetUImm12OpValue(MI, OpIdx, Fixups, MemSize); + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + return getOffsetUImm12OpValue(MI, OpIdx, Fixups, STI, MemSize); } unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI, int MemSize) const; unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRightImm8(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRightImm16(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRightImm32(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRightImm64(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftLeftImm8(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftLeftImm16(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftLeftImm32(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftLeftImm64(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // Labels are handled mostly the same way: a symbol is needed, and // just gets some fixup attached. template unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAddressWithFixup(const MCOperand &MO, unsigned FixupKind, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; void EmitByte(unsigned char C, raw_ostream &OS) const { @@ -125,11 +145,14 @@ public: const MCSubtargetInfo &STI) const; template unsigned - fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue) const; + fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const; - unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue) const; + unsigned fixMOVZ(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const; - unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue) const; + unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const; }; @@ -138,7 +161,8 @@ public: unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO, unsigned FixupKind, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (!MO.isExpr()) { // This can occur for manually decoded or constructed MCInsts, but neither // the assembly-parser nor instruction selection will currently produce an @@ -157,6 +181,7 @@ unsigned AArch64MCCodeEmitter::getAddressWithFixup(const MCOperand &MO, unsigned AArch64MCCodeEmitter:: getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI, int MemSize) const { const MCOperand &ImmOp = MI.getOperand(OpIdx); if (ImmOp.isImm()) @@ -237,12 +262,13 @@ getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx, break; } - return getAddressWithFixup(ImmOp, FixupKind, Fixups); + return getAddressWithFixup(ImmOp, FixupKind, Fixups, STI); } unsigned AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); if (MO.isImm()) return static_cast(MO.getImm()); @@ -270,12 +296,13 @@ AArch64MCCodeEmitter::getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx, FixupKind = AArch64::fixup_a64_tlsdesc_add_lo12_nc; break; } - return getAddressWithFixup(MO, FixupKind, Fixups); + return getAddressWithFixup(MO, FixupKind, Fixups, STI); } unsigned AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); if (MO.isImm()) @@ -305,12 +332,13 @@ AArch64MCCodeEmitter::getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx, llvm_unreachable("Unknown symbol reference kind for ADRP instruction"); } - return getAddressWithFixup(MO, FixupKind, Fixups); + return getAddressWithFixup(MO, FixupKind, Fixups, STI); } unsigned AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); assert(MO.isImm() && "Only immediate expected for shift"); @@ -320,7 +348,8 @@ AArch64MCCodeEmitter::getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx, unsigned AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); assert(MO.isImm() && "Only immediate expected for shift"); @@ -329,53 +358,62 @@ AArch64MCCodeEmitter::getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx, } unsigned AArch64MCCodeEmitter::getShiftRightImm8( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 8 - MI.getOperand(Op).getImm(); } unsigned AArch64MCCodeEmitter::getShiftRightImm16( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 16 - MI.getOperand(Op).getImm(); } unsigned AArch64MCCodeEmitter::getShiftRightImm32( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 32 - MI.getOperand(Op).getImm(); } unsigned AArch64MCCodeEmitter::getShiftRightImm64( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 64 - MI.getOperand(Op).getImm(); } unsigned AArch64MCCodeEmitter::getShiftLeftImm8( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return MI.getOperand(Op).getImm() - 8; } unsigned AArch64MCCodeEmitter::getShiftLeftImm16( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return MI.getOperand(Op).getImm() - 16; } unsigned AArch64MCCodeEmitter::getShiftLeftImm32( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return MI.getOperand(Op).getImm() - 32; } unsigned AArch64MCCodeEmitter::getShiftLeftImm64( - const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { + const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return MI.getOperand(Op).getImm() - 64; } template unsigned AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); if (MO.isExpr()) - return getAddressWithFixup(MO, fixupDesired, Fixups); + return getAddressWithFixup(MO, fixupDesired, Fixups, STI); assert(MO.isImm()); return MO.getImm(); @@ -384,7 +422,8 @@ AArch64MCCodeEmitter::getLabelOpValue(const MCInst &MI, unsigned AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); if (MO.isImm()) @@ -402,14 +441,15 @@ AArch64MCCodeEmitter::getLoadLitLabelOpValue(const MCInst &MI, FixupKind = AArch64::fixup_a64_ld_prel; } - return getAddressWithFixup(MO, FixupKind, Fixups); + return getAddressWithFixup(MO, FixupKind, Fixups, STI); } unsigned AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) { return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); } else if (MO.isImm()) { @@ -422,7 +462,8 @@ AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, unsigned AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &UImm16MO = MI.getOperand(OpIdx); const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1); @@ -483,12 +524,13 @@ AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx, requestedFixup = AArch64::fixup_a64_movw_tprel_g0_nc; break; } - return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups); + return Result | getAddressWithFixup(UImm16MO, requestedFixup, Fixups, STI); } template unsigned AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, - unsigned EncodedValue) const { + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { if (!hasRs) EncodedValue |= 0x001F0000; if (!hasRt2) EncodedValue |= 0x00007C00; @@ -496,7 +538,8 @@ AArch64MCCodeEmitter::fixLoadStoreExclusive(const MCInst &MI, } unsigned -AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const { +AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const { // If one of the signed fixup kinds is applied to a MOVZ instruction, the // eventual result could be either a MOVZ or a MOVN. It's the MCCodeEmitter's // job to ensure that any bits possibly affected by this are 0. This means we @@ -530,7 +573,8 @@ AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue) const { unsigned AArch64MCCodeEmitter::fixMulHigh(const MCInst &MI, - unsigned EncodedValue) const { + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { // The Ra field of SMULH and UMULH is unused: it should be assembled as 31 // (i.e. all bits 1) but is ignored by the processor. EncodedValue |= 0x1f << 10; @@ -559,7 +603,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, return; } - uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); + uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); EmitInstruction(Binary, OS); } diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp index 7a3cb1e2595..6fc909a6962 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp @@ -67,107 +67,131 @@ public: // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of /// the specified operand. This is used for operands with :lower16: and /// :upper16: prefixes. uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getThumbBLTargetOpValue - Return encoding info for Thumb immediate /// BL branch target. uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getThumbBLXTargetOpValue - Return encoding info for Thumb immediate /// BLX branch target. uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getBranchTargetOpValue - Return encoding info for 24-bit immediate /// branch target. uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getUnconditionalBranchTargetOpValue - Return encoding info for 24-bit /// immediate Thumb2 direct branch target. uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getARMBranchTargetOpValue - Return encoding info for 24-bit immediate /// branch target. uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint32_t getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint32_t getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAdrLabelOpValue - Return encoding info for 12-bit immediate /// ADR label target. uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint32_t getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' /// operand. uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getThumbAddrModeRegRegOpValue - Return encoding for 'reg + reg' operand. uint32_t getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups)const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getT2AddrModeImm8s4OpValue - Return encoding info for 'reg +/- imm8<<2' /// operand. uint32_t getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getT2AddrModeImm0_1020s4OpValue - Return encoding info for 'reg + imm8<<2' /// operand. uint32_t getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getT2Imm8s4OpValue - Return encoding info for '+/- imm8<<2' /// operand. uint32_t getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm' /// operand as needed by load/store instructions. uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getLdStmModeOpValue - Return encoding for load/store multiple mode. uint32_t getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); switch (Mode) { default: llvm_unreachable("Unknown addressing sub-mode!"); @@ -193,44 +217,54 @@ public: /// getAddrMode2OpValue - Return encoding for addrmode2 operands. uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands. uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getPostIdxRegOpValue - Return encoding for postidx_reg operands. uint32_t getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrMode3OffsetOpValue - Return encoding for am3offset operands. uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrMode3OpValue - Return encoding for addrmode3 operands. uint32_t getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrModeThumbSPOpValue - Return encoding info for 'reg +/- imm12' /// operand. uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. uint32_t getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand. uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getCCOutOpValue - Return encoding of the 's' bit. unsigned getCCOutOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or // '1' respectively. return MI.getOperand(Op).getReg() == ARM::CPSR; @@ -238,7 +272,8 @@ public: /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value. unsigned getSOImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { unsigned SoImm = MI.getOperand(Op).getImm(); int SoImmVal = ARM_AM::getSOImmVal(SoImm); assert(SoImmVal != -1 && "Not a valid so_imm value!"); @@ -254,7 +289,8 @@ public: /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value. unsigned getT2SOImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { unsigned SoImm = MI.getOperand(Op).getImm(); unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm); assert(Encoded != ~0U && "Not a Thumb2 so_imm value?"); @@ -262,64 +298,88 @@ public: } unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getSORegOpValue - Return an encoded so_reg shifted register value. unsigned getSORegRegOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getSORegImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 64 - MI.getOperand(Op).getImm(); } unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getThumbSRImmOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned NEONThumb2DataIPostEncoder(const MCInst &MI, - unsigned EncodedValue) const; + unsigned EncodedValue, + const MCSubtargetInfo &STI) const; unsigned NEONThumb2LoadStorePostEncoder(const MCInst &MI, - unsigned EncodedValue) const; + unsigned EncodedValue, + const MCSubtargetInfo &STI) const; unsigned NEONThumb2DupPostEncoder(const MCInst &MI, - unsigned EncodedValue) const; + unsigned EncodedValue, + const MCSubtargetInfo &STI) const; unsigned NEONThumb2V8PostEncoder(const MCInst &MI, - unsigned EncodedValue) const; + unsigned EncodedValue, + const MCSubtargetInfo &STI) const; unsigned VFPThumb2PostEncoder(const MCInst &MI, - unsigned EncodedValue) const; + unsigned EncodedValue, + const MCSubtargetInfo &STI) const; void EmitByte(unsigned char C, raw_ostream &OS) const { OS << (char)C; @@ -351,7 +411,8 @@ MCCodeEmitter *llvm::createARMMCCodeEmitter(const MCInstrInfo &MCII, /// instructions, and rewrite them to their Thumb2 form if we are currently in /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, - unsigned EncodedValue) const { + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { if (isThumb2()) { // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are @@ -370,7 +431,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, /// instructions, and rewrite them to their Thumb2 form if we are currently in /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, - unsigned EncodedValue) const { + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { if (isThumb2()) { EncodedValue &= 0xF0FFFFFF; EncodedValue |= 0x09000000; @@ -383,7 +445,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, /// instructions, and rewrite them to their Thumb2 form if we are currently in /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, - unsigned EncodedValue) const { + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { if (isThumb2()) { EncodedValue &= 0x00FFFFFF; EncodedValue |= 0xEE000000; @@ -395,7 +458,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form /// if we are in Thumb2. unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, - unsigned EncodedValue) const { + unsigned EncodedValue, + const MCSubtargetInfo &STI) const { if (isThumb2()) { EncodedValue |= 0xC000000; // Set bits 27-26 } @@ -406,7 +470,8 @@ unsigned ARMMCCodeEmitter::NEONThumb2V8PostEncoder(const MCInst &MI, /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite /// them to their Thumb2 form if we are currently in Thumb2 mode. unsigned ARMMCCodeEmitter:: -VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { +VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue, + const MCSubtargetInfo &STI) const { if (isThumb2()) { EncodedValue &= 0x0FFFFFFF; EncodedValue |= 0xE0000000; @@ -418,7 +483,8 @@ VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { /// operand requires relocation, record the relocation and return zero. unsigned ARMMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) { unsigned Reg = MO.getReg(); unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); @@ -446,7 +512,8 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand. bool ARMMCCodeEmitter:: EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, - unsigned &Imm, SmallVectorImpl &Fixups) const { + unsigned &Imm, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx + 1); @@ -475,7 +542,8 @@ EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, /// which is either an immediate or requires a fixup. static uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, - SmallVectorImpl &Fixups) { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) { const MCOperand &MO = MI.getOperand(OpIdx); // If the destination is an immediate, we have nothing to do. @@ -511,11 +579,12 @@ static int32_t encodeThumbBLOffset(int32_t offset) { /// getThumbBLTargetOpValue - Return encoding info for immediate branch target. uint32_t ARMMCCodeEmitter:: getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bl, - Fixups); + Fixups, STI); return encodeThumbBLOffset(MO.getImm()); } @@ -523,43 +592,47 @@ getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, /// BLX branch target. uint32_t ARMMCCodeEmitter:: getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_blx, - Fixups); + Fixups, STI); return encodeThumbBLOffset(MO.getImm()); } /// getThumbBRTargetOpValue - Return encoding info for Thumb branch target. uint32_t ARMMCCodeEmitter:: getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_br, - Fixups); + Fixups, STI); return (MO.getImm() >> 1); } /// getThumbBCCTargetOpValue - Return encoding info for Thumb branch target. uint32_t ARMMCCodeEmitter:: getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_bcc, - Fixups); + Fixups, STI); return (MO.getImm() >> 1); } /// getThumbCBTargetOpValue - Return encoding info for Thumb branch target. uint32_t ARMMCCodeEmitter:: getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cb, Fixups, STI); return (MO.getImm() >> 1); } @@ -584,27 +657,29 @@ static bool HasConditionalBranch(const MCInst &MI) { /// target. uint32_t ARMMCCodeEmitter:: getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // FIXME: This really, really shouldn't use TargetMachine. We don't want // coupling between MC and TM anywhere we can help it. if (isThumb2()) return - ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); - return getARMBranchTargetOpValue(MI, OpIdx, Fixups); + ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups, STI); + return getARMBranchTargetOpValue(MI, OpIdx, Fixups, STI); } /// getBranchTargetOpValue - Return encoding info for 24-bit immediate branch /// target. uint32_t ARMMCCodeEmitter:: getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) { if (HasConditionalBranch(MI)) return ::getBranchTargetOpValue(MI, OpIdx, - ARM::fixup_arm_condbranch, Fixups); + ARM::fixup_arm_condbranch, Fixups, STI); return ::getBranchTargetOpValue(MI, OpIdx, - ARM::fixup_arm_uncondbranch, Fixups); + ARM::fixup_arm_uncondbranch, Fixups, STI); } return MO.getImm() >> 2; @@ -612,13 +687,14 @@ getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) { if (HasConditionalBranch(MI)) return ::getBranchTargetOpValue(MI, OpIdx, - ARM::fixup_arm_condbl, Fixups); - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups); + ARM::fixup_arm_condbl, Fixups, STI); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_uncondbl, Fixups, STI); } return MO.getImm() >> 2; @@ -626,10 +702,11 @@ getARMBLTargetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_blx, Fixups, STI); return MO.getImm() >> 1; } @@ -638,12 +715,13 @@ getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, /// immediate branch target. uint32_t ARMMCCodeEmitter:: getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { unsigned Val = 0; const MCOperand MO = MI.getOperand(OpIdx); if(MO.isExpr()) - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_uncondbranch, Fixups, STI); else Val = MO.getImm() >> 1; @@ -667,11 +745,12 @@ getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, /// ADR label target. uint32_t ARMMCCodeEmitter:: getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_adr_pcrel_12, - Fixups); + Fixups, STI); int64_t offset = MO.getImm(); uint32_t Val = 0x2000; @@ -707,11 +786,12 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, /// target. uint32_t ARMMCCodeEmitter:: getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12, - Fixups); + Fixups, STI); int32_t Val = MO.getImm(); if (Val == INT32_MIN) Val = 0x1000; @@ -726,11 +806,12 @@ getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, /// target. uint32_t ARMMCCodeEmitter:: getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_thumb_adr_pcrel_10, - Fixups); + Fixups, STI); return MO.getImm(); } @@ -738,7 +819,8 @@ getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, /// operand. uint32_t ARMMCCodeEmitter:: getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &) const { + SmallVectorImpl &, + const MCSubtargetInfo &STI) const { // [Rn, Rm] // {5-3} = Rm // {2-0} = Rn @@ -752,7 +834,8 @@ getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand. uint32_t ARMMCCodeEmitter:: getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {17-13} = reg // {12} = (U)nsigned (add == '1', sub == '0') // {11-0} = imm12 @@ -789,7 +872,7 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, Imm12 = Offset; } } else - isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups); + isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups, STI); uint32_t Binary = Imm12 & 0xfff; // Immediate is always encoded as positive. The 'U' bit controls add vs sub. @@ -803,7 +886,8 @@ getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, /// '+/- imm8<<2' operand. uint32_t ARMMCCodeEmitter:: getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // FIXME: The immediate operand should have already been encoded like this // before ever getting here. The encoder method should just need to combine // the MI operands for the register and the offset into a single @@ -834,7 +918,8 @@ getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, /// 'reg +/- imm8<<2' operand. uint32_t ARMMCCodeEmitter:: getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {12-9} = reg // {8} = (U)nsigned (add == '1', sub == '0') // {7-0} = imm8 @@ -854,7 +939,7 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, ++MCNumCPRelocations; } else - isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); + isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); // FIXME: The immediate operand should have already been encoded like this // before ever getting here. The encoder method should just need to combine @@ -874,7 +959,8 @@ getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, /// 'reg + imm8<<2' operand. uint32_t ARMMCCodeEmitter:: getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {11-8} = reg // {7-0} = imm8 const MCOperand &MO = MI.getOperand(OpIdx); @@ -899,7 +985,8 @@ static bool EvaluateAsPCRel(const MCExpr *Expr) { uint32_t ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {20-16} = imm{15-12} // {11-0} = imm{11-0} const MCOperand &MO = MI.getOperand(OpIdx); @@ -972,7 +1059,8 @@ ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpIdx); const MCOperand &MO1 = MI.getOperand(OpIdx+1); const MCOperand &MO2 = MI.getOperand(OpIdx+2); @@ -1005,21 +1093,23 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {17-14} Rn // {13} 1 == imm12, 0 == Rm // {12} isAdd // {11-0} imm12/Rm const MCOperand &MO = MI.getOperand(OpIdx); unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); - uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups); + uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups, STI); Binary |= Rn << 14; return Binary; } uint32_t ARMMCCodeEmitter:: getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {13} 1 == imm12, 0 == Rm // {12} isAdd // {11-0} imm12/Rm @@ -1041,7 +1131,8 @@ getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {4} isAdd // {3-0} Rm const MCOperand &MO = MI.getOperand(OpIdx); @@ -1052,7 +1143,8 @@ getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {9} 1 == imm8, 0 == Rm // {8} isAdd // {7-4} imm7_4/zero @@ -1071,7 +1163,8 @@ getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, uint32_t ARMMCCodeEmitter:: getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {13} 1 == imm8, 0 == Rm // {12-9} Rn // {8} isAdd @@ -1107,7 +1200,8 @@ getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, /// getAddrModeThumbSPOpValue - Encode the t_addrmode_sp operands. uint32_t ARMMCCodeEmitter:: getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // [SP, #imm] // {7-0} = imm8 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); @@ -1122,7 +1216,8 @@ getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, /// getAddrModeISOpValue - Encode the t_addrmode_is# operands. uint32_t ARMMCCodeEmitter:: getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // [Rn, #imm] // {7-3} = imm5 // {2-0} = Rn @@ -1136,17 +1231,19 @@ getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, /// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands. uint32_t ARMMCCodeEmitter:: getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand MO = MI.getOperand(OpIdx); if (MO.isExpr()) - return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups); + return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_thumb_cp, Fixups, STI); return (MO.getImm() >> 2); } /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm10' operand. uint32_t ARMMCCodeEmitter:: getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // {12-9} = reg // {8} = (U)nsigned (add == '1', sub == '0') // {7-0} = imm8 @@ -1170,7 +1267,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, ++MCNumCPRelocations; } else { - EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups); + EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups, STI); isAdd = ARM_AM::getAM5Op(Imm8) == ARM_AM::add; } @@ -1184,7 +1281,8 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, unsigned ARMMCCodeEmitter:: getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be // shifted. The second is Rs, the amount to shift by, and the third specifies // the type of the shift. @@ -1231,7 +1329,8 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, unsigned ARMMCCodeEmitter:: getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Sub-operands are [reg, imm]. The first register is Rm, the reg to be // shifted. The second is the amount to shift by. // @@ -1277,7 +1376,8 @@ getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, unsigned ARMMCCodeEmitter:: getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO2 = MI.getOperand(OpNum+1); const MCOperand &MO3 = MI.getOperand(OpNum+2); @@ -1295,7 +1395,8 @@ getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, unsigned ARMMCCodeEmitter:: getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO1 = MI.getOperand(OpNum); const MCOperand &MO2 = MI.getOperand(OpNum+1); @@ -1316,7 +1417,8 @@ getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, unsigned ARMMCCodeEmitter:: getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO1 = MI.getOperand(OpNum); // FIXME: Needs fixup support. @@ -1332,7 +1434,8 @@ getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, unsigned ARMMCCodeEmitter:: getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO1 = MI.getOperand(OpNum); // FIXME: Needs fixup support. @@ -1348,7 +1451,8 @@ getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, unsigned ARMMCCodeEmitter:: getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Sub-operands are [reg, imm]. The first register is Rm, the reg to be // shifted. The second is the amount to shift by. // @@ -1390,7 +1494,8 @@ getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, unsigned ARMMCCodeEmitter:: getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the // msb of the mask. const MCOperand &MO = MI.getOperand(Op); @@ -1403,7 +1508,8 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op, unsigned ARMMCCodeEmitter:: getRegisterListOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // VLDM/VSTM: // {12-8} = Vd // {7-0} = Number of registers @@ -1439,7 +1545,8 @@ getRegisterListOpValue(const MCInst &MI, unsigned Op, /// with the alignment operand. unsigned ARMMCCodeEmitter:: getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Imm = MI.getOperand(Op + 1); @@ -1462,7 +1569,8 @@ getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, /// along with the alignment operand for use in VST1 and VLD1 with size 32. unsigned ARMMCCodeEmitter:: getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Imm = MI.getOperand(Op + 1); @@ -1488,7 +1596,8 @@ getAddrMode6OneLane32AddressOpValue(const MCInst &MI, unsigned Op, /// different for VLD4-dup. unsigned ARMMCCodeEmitter:: getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &Reg = MI.getOperand(Op); const MCOperand &Imm = MI.getOperand(Op + 1); @@ -1508,7 +1617,8 @@ getAddrMode6DupAddressOpValue(const MCInst &MI, unsigned Op, unsigned ARMMCCodeEmitter:: getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(Op); if (MO.getReg() == 0) return 0x0D; return CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); @@ -1516,25 +1626,29 @@ getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op, unsigned ARMMCCodeEmitter:: getShiftRight8Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 8 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: getShiftRight16Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 16 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: getShiftRight32Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 32 - MI.getOperand(Op).getImm(); } unsigned ARMMCCodeEmitter:: getShiftRight64Imm(const MCInst &MI, unsigned Op, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 64 - MI.getOperand(Op).getImm(); } @@ -1554,7 +1668,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, else llvm_unreachable("Unexpected instruction size!"); - uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); + uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI); // Thumb 32-bit wide instructions need to emit the high order halfword // first. if (isThumb() && Size == 4) { diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 12dd5c978a6..be8ccdac984 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -77,55 +77,68 @@ public: // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getBranchJumpOpValue - Return binary encoding of the jump // target operand. If the machine operand requires relocation, // record the relocation and return zero. unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump // target operand. If the machine operand requires relocation, // record the relocation and return zero. unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getBranchTargetOpValue - Return binary encoding of the branch // target operand. If the machine operand requires relocation, // record the relocation and return zero. unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getBranchTargetOpValue - Return binary encoding of the microMIPS branch // target operand. If the machine operand requires relocation, // record the relocation and return zero. unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getMachineOpValue - Return binary encoding of operand. If the machin // operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getSizeExtEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getLSAImmEncoding - Return binary encoding of LSA immediate. unsigned getLSAImmEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned - getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups) const; + getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; // class MipsMCCodeEmitter } // namespace @@ -240,7 +253,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, } unsigned long N = Fixups.size(); - uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups); + uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); // Check for unimplemented opcodes. // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 @@ -256,7 +269,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, Fixups.pop_back(); Opcode = NewOpcode; TmpInst.setOpcode (NewOpcode); - Binary = getBinaryCodeForInstr(TmpInst, Fixups); + Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI); } } @@ -275,7 +288,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, /// record the relocation and return zero. unsigned MipsMCCodeEmitter:: getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); @@ -296,7 +310,8 @@ getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, /// record the relocation and return zero. unsigned MipsMCCodeEmitter:: getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); @@ -318,7 +333,8 @@ getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, /// record the relocation and return zero. unsigned MipsMCCodeEmitter:: getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); // If the destination is an immediate, divide by 4. @@ -335,7 +351,8 @@ getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, unsigned MipsMCCodeEmitter:: getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); // If the destination is an immediate, divide by 2. @@ -351,7 +368,8 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, } unsigned MipsMCCodeEmitter:: -getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups) const { +getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { int64_t Res; if (Expr->EvaluateAsAbsolute(Res)) @@ -363,8 +381,8 @@ getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups) const { } if (Kind == MCExpr::Binary) { - unsigned Res = getExprOpValue(cast(Expr)->getLHS(), Fixups); - Res += getExprOpValue(cast(Expr)->getRHS(), Fixups); + unsigned Res = getExprOpValue(cast(Expr)->getLHS(), Fixups, STI); + Res += getExprOpValue(cast(Expr)->getRHS(), Fixups, STI); return Res; } if (Kind == MCExpr::SymbolRef) { @@ -471,7 +489,8 @@ getExprOpValue(const MCExpr *Expr,SmallVectorImpl &Fixups) const { /// operand requires relocation, record the relocation and return zero. unsigned MipsMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) { unsigned Reg = MO.getReg(); unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); @@ -484,18 +503,19 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, } // MO must be an Expr. assert(MO.isExpr()); - return getExprOpValue(MO.getExpr(),Fixups); + return getExprOpValue(MO.getExpr(),Fixups, STI); } /// getMSAMemEncoding - Return binary encoding of memory operand for LD/ST /// instructions. unsigned MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. assert(MI.getOperand(OpNo).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; - unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); // The immediate field of an LD/ST instruction is scaled which means it must // be divided (when encoding) by the size (in bytes) of the instructions' @@ -534,31 +554,34 @@ MipsMCCodeEmitter::getMSAMemEncoding(const MCInst &MI, unsigned OpNo, /// If the offset operand requires relocation, record the relocation. unsigned MipsMCCodeEmitter::getMemEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. assert(MI.getOperand(OpNo).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; - unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); return (OffBits & 0xFFFF) | RegBits; } unsigned MipsMCCodeEmitter:: getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. assert(MI.getOperand(OpNo).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) << 16; - unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); return (OffBits & 0x0FFF) | RegBits; } unsigned MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { assert(MI.getOperand(OpNo).isImm()); - unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); + unsigned SizeEncoding = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); return SizeEncoding - 1; } @@ -566,21 +589,23 @@ MipsMCCodeEmitter::getSizeExtEncoding(const MCInst &MI, unsigned OpNo, // unsigned MipsMCCodeEmitter::getSizeInsEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { assert(MI.getOperand(OpNo-1).isImm()); assert(MI.getOperand(OpNo).isImm()); - unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups); - unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups); + unsigned Position = getMachineOpValue(MI, MI.getOperand(OpNo-1), Fixups, STI); + unsigned Size = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI); return Position + Size - 1; } unsigned MipsMCCodeEmitter::getLSAImmEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { assert(MI.getOperand(OpNo).isImm()); // The immediate is encoded as 'immediate - 1'. - return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups) - 1; + return getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) - 1; } #include "MipsGenMCCodeEmitter.inc" diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 8b993a607be..f8b3c30001d 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -46,35 +46,47 @@ public: ~PPCMCCodeEmitter() {} unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getTLSRegEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getTLSCallEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { @@ -85,7 +97,7 @@ public: if (Opcode == TargetOpcode::COPY_TO_REGCLASS) return; - uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); + uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); // BL8_NOP etc. all have a size of 8 because of the following 'nop'. unsigned Size = 4; // FIXME: Have Desc.getSize() return the correct value! @@ -116,9 +128,10 @@ MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII, unsigned PPCMCCodeEmitter:: getDirectBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(0, MO.getExpr(), @@ -127,9 +140,10 @@ getDirectBrEncoding(const MCInst &MI, unsigned OpNo, } unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(0, MO.getExpr(), @@ -139,9 +153,10 @@ unsigned PPCMCCodeEmitter::getCondBrEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter:: getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(0, MO.getExpr(), @@ -151,9 +166,10 @@ getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter:: getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); // Add a fixup for the branch target. Fixups.push_back(MCFixup::Create(0, MO.getExpr(), @@ -162,9 +178,10 @@ getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, } unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); // Add a fixup for the immediate field. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), @@ -173,15 +190,16 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo, } unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Encode (imm, reg) as a memri, which has the low 16-bits as the // displacement and the next 5 bits as the register #. assert(MI.getOperand(OpNo+1).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; const MCOperand &MO = MI.getOperand(OpNo); if (MO.isImm()) - return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; + return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; // Add a fixup for the displacement field. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), @@ -191,15 +209,16 @@ unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // Encode (imm, reg) as a memrix, which has the low 14-bits as the // displacement and the next 5 bits as the register #. assert(MI.getOperand(OpNo+1).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; const MCOperand &MO = MI.getOperand(OpNo); if (MO.isImm()) - return ((getMachineOpValue(MI, MO, Fixups) >> 2) & 0x3FFF) | RegBits; + return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; // Add a fixup for the displacement field. Fixups.push_back(MCFixup::Create(2, MO.getExpr(), @@ -209,9 +228,10 @@ unsigned PPCMCCodeEmitter::getMemRIXEncoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); - if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups); + if (MO.isReg()) return getMachineOpValue(MI, MO, Fixups, STI); // Add a fixup for the TLS register, which simply provides a relocation // hint to the linker that this statement is part of a relocation sequence. @@ -223,19 +243,21 @@ unsigned PPCMCCodeEmitter::getTLSRegEncoding(const MCInst &MI, unsigned OpNo, } unsigned PPCMCCodeEmitter::getTLSCallEncoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { // For special TLS calls, we need two fixups; one for the branch target // (__tls_get_addr), which we create via getDirectBrEncoding as usual, // and one for the TLSGD or TLSLD symbol, which is emitted here. const MCOperand &MO = MI.getOperand(OpNo+1); Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)PPC::fixup_ppc_nofixup)); - return getDirectBrEncoding(MI, OpNo, Fixups); + return getDirectBrEncoding(MI, OpNo, Fixups, STI); } unsigned PPCMCCodeEmitter:: get_crbitm_encoding(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 || MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && @@ -246,7 +268,8 @@ get_crbitm_encoding(const MCInst &MI, unsigned OpNo, unsigned PPCMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) { // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand. // The GPR operand should come through here though. diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h index d8cf64adb91..ab2d74697d3 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -22,16 +22,19 @@ namespace llvm { class MCInst; class MCOperand; +class MCSubtargetInfo; class AMDGPUMCCodeEmitter : public MCCodeEmitter { virtual void anchor(); public: uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return 0; } }; diff --git a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp index 24609bb24df..63143382ace 100644 --- a/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/R600MCCodeEmitter.cpp @@ -49,7 +49,8 @@ public: /// \returns the encoding for an MCOperand. virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; private: void EmitByte(unsigned int byte, raw_ostream &OS) const; @@ -98,7 +99,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, MI.getOpcode() == AMDGPU::KILL) { return; } else if (IS_VTX(Desc)) { - uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups); + uint64_t InstWord01 = getBinaryCodeForInstr(MI, Fixups, STI); uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset if (!(STI.getFeatureBits() & AMDGPU::FeatureCaymanISA)) { InstWord2 |= 1 << 19; // Mega-Fetch bit @@ -122,7 +123,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, MI.getOperand(8).getImm() & 0x1F }; - uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups); + uint64_t Word01 = getBinaryCodeForInstr(MI, Fixups, STI); uint32_t Word2 = Sampler << 15 | SrcSelect[ELEMENT_X] << 20 | SrcSelect[ELEMENT_Y] << 23 | SrcSelect[ELEMENT_Z] << 26 | SrcSelect[ELEMENT_W] << 29 | Offsets[0] << 0 | Offsets[1] << 5 | @@ -132,7 +133,7 @@ void R600MCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, Emit(Word2, OS); Emit((uint32_t) 0, OS); } else { - uint64_t Inst = getBinaryCodeForInstr(MI, Fixups); + uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && ((Desc.TSFlags & R600_InstFlag::OP1) || Desc.TSFlags & R600_InstFlag::OP2)) { @@ -170,7 +171,8 @@ unsigned R600MCCodeEmitter::getHWReg(unsigned RegNo) const { uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixup) const { + SmallVectorImpl &Fixup, + const MCSubtargetInfo &STI) const { if (MO.isReg()) { if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) { return MRI.getEncodingValue(MO.getReg()); diff --git a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index 53dad5a08ca..130d2686b41 100644 --- a/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -60,7 +60,8 @@ public: /// \returns the encoding for an MCOperand. virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; } // End anonymous namespace @@ -129,7 +130,7 @@ void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups); + uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI); const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); unsigned bytes = Desc.getSize(); @@ -170,7 +171,8 @@ void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS, uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) return MRI.getEncodingValue(MO.getReg()); diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp index 22417e41215..8c318274a45 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp @@ -45,17 +45,21 @@ public: // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; }; } // end anonymous namespace @@ -71,7 +75,7 @@ void SparcMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - unsigned Bits = getBinaryCodeForInstr(MI, Fixups); + unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); // Output the constant in big endian byte order. for (unsigned i = 0; i != 4; ++i) { @@ -85,7 +89,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, unsigned SparcMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); @@ -140,10 +145,11 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, unsigned SparcMCCodeEmitter:: getCallTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) - return getMachineOpValue(MI, MO, Fixups); + return getMachineOpValue(MI, MO, Fixups, STI); Fixups.push_back(MCFixup::Create(0, MO.getExpr(), (MCFixupKind)Sparc::fixup_sparc_call30)); @@ -152,10 +158,11 @@ getCallTargetOpValue(const MCInst &MI, unsigned OpNo, unsigned SparcMCCodeEmitter:: getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { const MCOperand &MO = MI.getOperand(OpNo); if (MO.isReg() || MO.isImm()) - return getMachineOpValue(MI, MO, Fixups); + return getMachineOpValue(MI, MO, Fixups, STI); Sparc::Fixups fixup = Sparc::fixup_sparc_br22; if (MI.getOpcode() == SP::BPXCC) diff --git a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp index d7ac2379dcb..84dc47300ca 100644 --- a/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp +++ b/lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp @@ -42,27 +42,34 @@ public: private: // Automatically generated by TableGen. uint64_t getBinaryCodeForInstr(const MCInst &MI, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // Called by the TableGen code to get the binary encoding of operand // MO in MI. Fixups is the list of fixups against MI. uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // Called by the TableGen code to get the binary encoding of an address. // The index or length, if any, is encoded first, followed by the base, // followed by the displacement. In a 20-bit displacement, // the low 12 bits are encoded before the high 8 bits. uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; // Operand OpNum of MI needs a PC-relative fixup of kind Kind at // Offset bytes from the start of MI. Add the fixup to Fixups @@ -73,11 +80,13 @@ private: unsigned Kind, int64_t Offset) const; uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2); } uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2); } }; @@ -94,7 +103,7 @@ void SystemZMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { - uint64_t Bits = getBinaryCodeForInstr(MI, Fixups); + uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); unsigned Size = MCII.get(MI.getOpcode()).getSize(); // Big-endian insertion of Size bytes. unsigned ShiftValue = (Size * 8) - 8; @@ -106,7 +115,8 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, uint64_t SystemZMCCodeEmitter:: getMachineOpValue(const MCInst &MI, const MCOperand &MO, - SmallVectorImpl &Fixups) const { + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); if (MO.isImm()) @@ -116,38 +126,42 @@ getMachineOpValue(const MCInst &MI, const MCOperand &MO, uint64_t SystemZMCCodeEmitter:: getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); assert(isUInt<4>(Base) && isUInt<12>(Disp)); return (Base << 12) | Disp; } uint64_t SystemZMCCodeEmitter:: getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); assert(isUInt<4>(Base) && isInt<20>(Disp)); return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); } uint64_t SystemZMCCodeEmitter:: getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); - uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); return (Index << 16) | (Base << 12) | Disp; } uint64_t SystemZMCCodeEmitter:: getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); - uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups); + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); @@ -155,10 +169,11 @@ getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, uint64_t SystemZMCCodeEmitter:: getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, - SmallVectorImpl &Fixups) const { - uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups); - uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups); - uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1; + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); + uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); + uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1; assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); return (Len << 16) | (Base << 12) | Disp; } diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index b7dea1046ba..a4ff4eec1e4 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -122,14 +122,14 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, Case += " // op: " + VarName + "\n" + " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); if (MCEmitter) - Case += ", Fixups"; + Case += ", Fixups, STI"; Case += ");\n"; } } else { Case += " // op: " + VarName + "\n" + " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; if (MCEmitter) - Case += ", Fixups"; + Case += ", Fixups, STI"; Case += ");\n"; } @@ -192,8 +192,12 @@ std::string CodeEmitterGen::getInstructionCase(Record *R, } std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); - if (!PostEmitter.empty()) - Case += " Value = " + PostEmitter + "(MI, Value);\n"; + if (!PostEmitter.empty()) { + Case += " Value = " + PostEmitter + "(MI, Value"; + if (MCEmitter) + Case += ", STI"; + Case += ");\n"; + } return Case; } @@ -212,7 +216,8 @@ void CodeEmitterGen::run(raw_ostream &o) { o << "uint64_t " << Target.getName(); if (MCEmitter) o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" - << " SmallVectorImpl &Fixups) const {\n"; + << " SmallVectorImpl &Fixups,\n" + << " const MCSubtargetInfo &STI) const {\n"; else o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n";