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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Now support instructions with implicit write to non-flag registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24878 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
7226158d7e
commit
4fba28116c
@ -1763,7 +1763,6 @@ private:
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// Names of all the folded nodes which produce chains.
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std::vector<std::pair<std::string, unsigned> > FoldedChains;
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bool FoundChain;
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bool InFlag;
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unsigned TmpNo;
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public:
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@ -1771,7 +1770,7 @@ public:
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TreePatternNode *pattern, TreePatternNode *instr,
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unsigned PatNum, std::ostream &os) :
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ISE(ise), Predicates(preds), Pattern(pattern), Instruction(instr),
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PatternNo(PatNum), OS(os), FoundChain(false), InFlag(false), TmpNo(0) {};
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PatternNo(PatNum), OS(os), FoundChain(false), TmpNo(0) {};
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/// EmitMatchCode - Emit a matcher for N, going to the label for PatternNo
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/// if the match fails. At this point, we already know that the opcode for N
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@ -1884,10 +1883,6 @@ public:
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if (LeafRec->isSubClassOf("RegisterClass")) {
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// Handle register references. Nothing to do here.
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} else if (LeafRec->isSubClassOf("Register")) {
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if (!InFlag) {
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OS << " SDOperand InFlag = SDOperand(0,0);\n";
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InFlag = true;
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}
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} else if (LeafRec->isSubClassOf("ComplexPattern")) {
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// Handle complex pattern. Nothing to do here.
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} else if (LeafRec->getName() == "srcvalue") {
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@ -2015,6 +2010,16 @@ public:
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Record *Op = N->getOperator();
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if (Op->isSubClassOf("Instruction")) {
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const DAGInstruction &Inst = ISE.getInstruction(Op);
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unsigned NumImpResults = Inst.getNumImpResults();
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unsigned NumImpOperands = Inst.getNumImpOperands();
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bool InFlag = NumImpOperands > 0;
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bool OutFlag = NumImpResults > 0;
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bool IsCopyFromReg = false;
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if (InFlag || OutFlag)
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OS << " SDOperand InFlag = SDOperand(0,0);\n";
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// Determine operand emission order. Complex pattern first.
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std::vector<std::pair<unsigned, TreePatternNode*> > EmitOrder;
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std::vector<std::pair<unsigned, TreePatternNode*> >::iterator OI;
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@ -2052,10 +2057,9 @@ public:
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// Emit all the chain and CopyToReg stuff.
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if (II.hasCtrlDep)
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OS << " Chain = Select(Chain);\n";
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EmitCopyToRegs(Pattern, "N", II.hasCtrlDep);
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if (InFlag)
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EmitCopyToRegs(Pattern, "N", II.hasCtrlDep);
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const DAGInstruction &Inst = ISE.getInstruction(Op);
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unsigned NumImpResults = Inst.getNumImpResults();
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unsigned NumResults = Inst.getNumResults();
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unsigned ResNo = TmpNo++;
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if (!isRoot) {
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@ -2063,11 +2067,8 @@ public:
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<< II.Namespace << "::" << II.TheDef->getName();
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if (N->getType() != MVT::isVoid)
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OS << ", MVT::" << getEnumName(N->getType());
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for (unsigned i = 0; i < NumImpResults; i++) {
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Record *ImpResult = Inst.getImpResult(i);
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MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
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OS << ", MVT::" << getEnumName(RVT);
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}
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if (OutFlag)
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OS << ", MVT::Flag";
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unsigned LastOp = 0;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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@ -2080,7 +2081,7 @@ public:
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OS << " Chain = Tmp" << LastOp << ".getValue("
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<< NumResults << ");\n";
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}
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} else if (II.hasCtrlDep || NumImpResults > 0) {
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} else if (II.hasCtrlDep || OutFlag) {
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OS << " SDOperand Result = CurDAG->getTargetNode("
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<< II.Namespace << "::" << II.TheDef->getName();
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@ -2093,11 +2094,8 @@ public:
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}
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if (II.hasCtrlDep)
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OS << ", MVT::Other";
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for (unsigned i = 0; i < NumImpResults; i++) {
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Record *ImpResult = Inst.getImpResult(i);
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MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
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OS << ", MVT::" << getEnumName(RVT);
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}
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if (OutFlag)
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OS << ", MVT::Flag";
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// Inputs.
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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@ -2114,33 +2112,43 @@ public:
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}
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if (II.hasCtrlDep) {
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OS << " Chain ";
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if (NodeHasChain(Pattern, ISE))
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OS << "= CodeGenMap[N.getValue(" << ValNo + NumImpResults << ")] ";
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OS << " Chain = Result.getValue(" << ValNo << ");\n";
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if (OutFlag)
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OS << " InFlag = Result.getValue(" << ValNo+1 << ");\n";
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} else if (OutFlag)
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OS << " InFlag = Result.getValue(" << ValNo << ");\n";
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if (OutFlag)
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IsCopyFromReg = EmitCopyFromRegs(N, II.hasCtrlDep);
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if (IsCopyFromReg)
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OS << " CodeGenMap[N.getValue(" << ValNo++ << ")] = Result;\n";
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if (OutFlag)
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OS << " CodeGenMap[N.getValue(" << ValNo++ << ")] = InFlag;\n";
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if (IsCopyFromReg || II.hasCtrlDep) {
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OS << " ";
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if (IsCopyFromReg || NodeHasChain(Pattern, ISE))
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OS << "CodeGenMap[N.getValue(" << ValNo << ")] = ";
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for (unsigned j = 0, e = FoldedChains.size(); j < e; j++)
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OS << "= CodeGenMap[" << FoldedChains[j].first << ".getValue("
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<< FoldedChains[j].second << ")] ";
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OS << "= Result.getValue(" << ValNo << ");\n";
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for (unsigned i = 0; i < NumImpResults; i++) {
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OS << " CodeGenMap[N.getValue(" << ValNo << ")] = Result";
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OS << ".getValue(" << ValNo+1 << ");\n";
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ValNo++;
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}
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} else {
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for (unsigned i = 0; i < NumImpResults; i++) {
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OS << " CodeGenMap[N.getValue(" << ValNo << ")] = Result";
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OS << ".getValue(" << ValNo << ");\n";
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ValNo++;
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}
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OS << "CodeGenMap[" << FoldedChains[j].first << ".getValue("
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<< FoldedChains[j].second << ")] = ";
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OS << "Chain;\n";
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}
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// FIXME: this only works because (for now) an instruction can either
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// produce a single result or a single flag.
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if (II.hasCtrlDep && NumImpResults > 0)
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OS << " return (N.ResNo) ? Chain : Result.getValue(1);"
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<< " // Chain comes before flag.\n";
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else
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if (II.hasCtrlDep && OutFlag) {
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if (IsCopyFromReg)
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OS << " return (N.ResNo == 0) ? Result : "
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<< "((N.ResNo == 2) ? Chain : InFlag);"
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<< " // Chain comes before flag.\n";
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else
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OS << " return (N.ResNo) ? Chain : InFlag;"
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<< " // Chain comes before flag.\n";
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} else {
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OS << " return Result.getValue(N.ResNo);\n";
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}
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} else {
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// If this instruction is the root, and if there is only one use of it,
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// use SelectNodeTo instead of getTargetNode to avoid an allocation.
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@ -2149,11 +2157,8 @@ public:
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<< II.Namespace << "::" << II.TheDef->getName();
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if (N->getType() != MVT::isVoid)
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OS << ", MVT::" << getEnumName(N->getType());
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for (unsigned i = 0; i < NumImpResults; i++) {
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Record *ImpResult = Inst.getImpResult(i);
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MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
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OS << ", MVT::" << getEnumName(RVT);
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}
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if (OutFlag)
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OS << ", MVT::Flag";
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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OS << ", Tmp" << Ops[i];
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if (InFlag)
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@ -2164,11 +2169,8 @@ public:
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<< II.Namespace << "::" << II.TheDef->getName();
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if (N->getType() != MVT::isVoid)
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OS << ", MVT::" << getEnumName(N->getType());
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for (unsigned i = 0; i < NumImpResults; i++) {
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Record *ImpResult = Inst.getImpResult(i);
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MVT::ValueType RVT = getRegisterValueType(ImpResult, CGT);
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OS << ", MVT::" << getEnumName(RVT);
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}
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if (OutFlag)
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OS << ", MVT::Flag";
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for (unsigned i = 0, e = Ops.size(); i != e; ++i)
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OS << ", Tmp" << Ops[i];
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if (InFlag)
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@ -2176,6 +2178,7 @@ public:
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OS << ");\n";
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OS << " }\n";
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}
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return std::make_pair(1, ResNo);
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} else if (Op->isSubClassOf("SDNodeXForm")) {
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assert(N->getNumChildren() == 1 && "node xform should have one child!");
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@ -2259,6 +2262,43 @@ private:
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}
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}
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}
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/// EmitCopyFromRegs - Emit code to copy result to physical registers
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/// as specified by the instruction.
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bool EmitCopyFromRegs(TreePatternNode *N, bool HasCtrlDep) {
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bool RetVal = false;
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Record *Op = N->getOperator();
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if (Op->isSubClassOf("Instruction")) {
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const DAGInstruction &Inst = ISE.getInstruction(Op);
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const CodeGenTarget &CGT = ISE.getTargetInfo();
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CodeGenInstruction &II = CGT.getInstruction(Op->getName());
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unsigned NumImpResults = Inst.getNumImpResults();
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for (unsigned i = 0; i < NumImpResults; i++) {
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Record *RR = Inst.getImpResult(i);
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if (RR->isSubClassOf("Register")) {
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MVT::ValueType RVT = getRegisterValueType(RR, CGT);
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if (RVT != MVT::Flag) {
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if (HasCtrlDep) {
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OS << " Result = CurDAG->getCopyFromReg(Chain, "
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<< ISE.getQualifiedName(RR)
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<< ", MVT::" << getEnumName(RVT) << ", InFlag);\n";
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OS << " Chain = Result.getValue(1);\n";
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OS << " InFlag = Result.getValue(2);\n";
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} else {
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OS << " SDOperand Chain;\n";
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OS << " Result = CurDAG->getCopyFromReg("
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<< "CurDAG->getEntryNode(), ISE.getQualifiedName(RR)"
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<< ", MVT::" << getEnumName(RVT) << ", InFlag);\n";
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OS << " Chain = Result.getValue(1);\n";
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OS << " InFlag = Result.getValue(2);\n";
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}
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RetVal = true;
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}
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}
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}
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}
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return RetVal;
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}
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};
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/// EmitCodeForPattern - Given a pattern to match, emit code to the specified
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