From 4fcfcf498436533ea9bc59404d10751bc76cfd2c Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 14 Jul 2011 00:58:38 +0000 Subject: [PATCH] Revert r135121 which broke a gcc-4.2 builder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135122 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/InterferenceCache.cpp | 17 +++--------- lib/CodeGen/InterferenceCache.h | 43 +++---------------------------- lib/CodeGen/RegAllocGreedy.cpp | 21 ++++----------- 3 files changed, 11 insertions(+), 70 deletions(-) diff --git a/lib/CodeGen/InterferenceCache.cpp b/lib/CodeGen/InterferenceCache.cpp index a09bb39f833..b1014a97fa0 100644 --- a/lib/CodeGen/InterferenceCache.cpp +++ b/lib/CodeGen/InterferenceCache.cpp @@ -14,7 +14,6 @@ #define DEBUG_TYPE "regalloc" #include "InterferenceCache.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Support/ErrorHandling.h" using namespace llvm; @@ -41,18 +40,9 @@ InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) { E = RoundRobin; if (++RoundRobin == CacheEntries) RoundRobin = 0; - for (unsigned i = 0; i != CacheEntries; ++i) { - // Skip entries that are in use. - if (Entries[E].hasRefs()) { - if (++E == CacheEntries) - E = 0; - continue; - } - Entries[E].reset(PhysReg, LIUArray, TRI, MF); - PhysRegEntries[PhysReg] = E; - return &Entries[E]; - } - llvm_unreachable("Ran out of interference cache entries."); + Entries[E].reset(PhysReg, LIUArray, TRI, MF); + PhysRegEntries[PhysReg] = E; + return &Entries[E]; } /// revalidate - LIU contents have changed, update tags. @@ -69,7 +59,6 @@ void InterferenceCache::Entry::reset(unsigned physReg, LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI, const MachineFunction *MF) { - assert(!hasRefs() && "Cannot reset cache entry with references"); // LIU's changed, invalidate cache. ++Tag; PhysReg = physReg; diff --git a/lib/CodeGen/InterferenceCache.h b/lib/CodeGen/InterferenceCache.h index 2f402e4048b..6434b3a788d 100644 --- a/lib/CodeGen/InterferenceCache.h +++ b/lib/CodeGen/InterferenceCache.h @@ -43,9 +43,6 @@ class InterferenceCache { /// change. unsigned Tag; - /// RefCount - The total number of Cursor instances referring to this Entry. - unsigned RefCount; - /// MF - The current function. MachineFunction *MF; @@ -71,10 +68,9 @@ class InterferenceCache { void update(unsigned MBBNum); public: - Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {} + Entry() : PhysReg(0), Tag(0), Indexes(0) {} void clear(MachineFunction *mf, SlotIndexes *indexes) { - assert(!hasRefs() && "Cannot clear cache entry with references"); PhysReg = 0; MF = mf; Indexes = indexes; @@ -82,10 +78,6 @@ class InterferenceCache { unsigned getPhysReg() const { return PhysReg; } - void addRef(int Delta) { RefCount += Delta; } - - bool hasRefs() const { return RefCount > 0; } - void revalidate(); /// valid - Return true if this is a valid entry for physReg. @@ -130,47 +122,18 @@ public: void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*, const TargetRegisterInfo *); - /// getMaxCursors - Return the maximum number of concurrent cursors that can - /// be supported. - unsigned getMaxCursors() const { return CacheEntries; } - /// Cursor - The primary query interface for the block interference cache. class Cursor { Entry *CacheEntry; BlockInterference *Current; - - void setEntry(Entry *E) { - // Update reference counts. Nothing happens when RefCount reaches 0, so - // we don't have to check for E == CacheEntry etc. - if (CacheEntry) - CacheEntry->addRef(-1); - CacheEntry = E; - if (CacheEntry) - CacheEntry->addRef(+1); - Current = 0; - } - public: /// Cursor - Create a dangling cursor. Cursor() : CacheEntry(0), Current(0) {} - ~Cursor() { setEntry(0); } - - Cursor(const Cursor &O) { - setEntry(O.CacheEntry); - } - - Cursor &operator=(const Cursor &O) { - setEntry(O.CacheEntry); - return *this; - } /// setPhysReg - Point this cursor to PhysReg's interference. void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) { - // Release reference before getting a new one. That guarantees we can - // actually have CacheEntries live cursors. - setEntry(0); - if (PhysReg) - setEntry(Cache.get(PhysReg)); + CacheEntry = Cache.get(PhysReg); + Current = 0; } /// moveTo - Move cursor to basic block MBBNum. diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 8677a3e257a..4728a050b17 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -854,6 +854,11 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, }); InterferenceCache::Cursor &Intf = Cand.Intf; + + // FIXME: We need cache reference counts to guarantee that Intf hasn't been + // clobbered. + Intf.setPhysReg(IntfCache, Cand.PhysReg); + LiveRangeEdit LREdit(VirtReg, NewVRegs, this); SE->reset(LREdit); @@ -1247,22 +1252,6 @@ unsigned RAGreedy::tryRegionSplit(LiveInterval &VirtReg, AllocationOrder &Order, Order.rewind(); while (unsigned PhysReg = Order.next()) { - // Discard bad candidates before we run out of interference cache cursors. - // This will only affect register classes with a lot of registers (>32). - if (NumCands == IntfCache.getMaxCursors()) { - unsigned WorstCount = ~0u; - unsigned Worst = 0; - for (unsigned i = 0; i != NumCands; ++i) { - if (i == BestCand) - continue; - unsigned Count = GlobalCand[i].LiveBundles.count(); - if (Count < WorstCount) - Worst = i, WorstCount = Count; - } - --NumCands; - GlobalCand[Worst] = GlobalCand[NumCands]; - } - if (GlobalCand.size() <= NumCands) GlobalCand.resize(NumCands+1); GlobalSplitCandidate &Cand = GlobalCand[NumCands];