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Another 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101620 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1385,7 +1385,8 @@ void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
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if (NVTBits < EVTBits) {
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Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
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DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(), EVTBits - NVTBits)));
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DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
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EVTBits - NVTBits)));
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} else {
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Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
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// The high part replicates the sign bit of Lo, make it explicit.
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