6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-10-31 09:11:13 +00:00
Code Issues Projects Releases Wiki Activity

Add mem forms of AND instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11521 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-17 05:25:50 +00:00
parent 7093d37304
commit 4ff7876c64
3 changed files with 71 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
lib/Target/X86/PeepholeOptimizer.cpp
View File

@ -109,9 +109,9 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
unsigned R1 = MI->getOperand(1).getReg();
unsigned Scale = MI->getOperand(2).getImmedValue();
unsigned R2 = MI->getOperand(3).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
unsigned Offset = MI->getOperand(4).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
@ -146,6 +146,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
case X86::XORri32: Opcode = X86::XORri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned Scale = MI->getOperand(1).getImmedValue();
unsigned R1 = MI->getOperand(2).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
addReg(R1).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
case X86::ANDmi16: case X86::ANDmi32:
assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
if (MI->getOperand(4).isImmediate()) {
int Val = MI->getOperand(4).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::ANDmi16: Opcode = X86::ANDmi16b; break;
case X86::ANDmi32: Opcode = X86::ANDmi32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val));
return true;

19
lib/Target/X86/X86InstrInfo.td
View File

@ -319,11 +319,26 @@ def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >; // R32 =
def ANDrr8 : I2A8 <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>;
def ANDrr16 : I2A16<"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>;
def ANDrr32 : I2A32<"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>;
def ANDmr8 : I2A8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
def ANDmr16 : I2A16<"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
def ANDmr32 : I2A32<"and", 0x21, MRMDestMem>; // [mem32] &= R32
def ANDrm8 : I2A8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8]
def ANDrm16 : I2A16<"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16]
def ANDrm32 : I2A32<"and", 0x23, MRMSrcMem >; // R32 &= [mem32]
def ANDri8 : I2A8 <"and", 0x80, MRMS4r >, Pattern<(set R8 , (and R8 , imm))>;
def ANDri16 : I2A16<"and", 0x81, MRMS4r >, OpSize, Pattern<(set R16, (and R16, imm))>;
def ANDri32 : I2A32<"and", 0x81, MRMS4r >, Pattern<(set R32, (and R32, imm))>;
def ANDri16b : I2A8 <"and", 0x83, MRMS4r >, OpSize;
def ANDri32b : I2A8 <"and", 0x83, MRMS4r >;
def ANDmi8 : I2A8 <"and", 0x80, MRMS4m >; // [mem8] &= imm8
def ANDmi16 : I2A16<"and", 0x81, MRMS4m >, OpSize; // [mem16] &= imm16
def ANDmi32 : I2A32<"and", 0x81, MRMS4m >; // [mem32] &= imm32
def ANDri16b : I2A8 <"and", 0x83, MRMS4r >, OpSize; // R16 &= imm8
def ANDri32b : I2A8 <"and", 0x83, MRMS4r >; // R32 &= imm8
def ANDmi16b : I2A8 <"and", 0x83, MRMS4m >, OpSize; // [mem16] &= imm8
def ANDmi32b : I2A8 <"and", 0x83, MRMS4m >; // [mem32] &= imm8
def ORrr8 : I2A8 <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>;
def ORrr16 : I2A16<"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>;

29
lib/Target/X86/X86PeepholeOpt.cpp
View File

@ -109,9 +109,9 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
unsigned R1 = MI->getOperand(1).getReg();
unsigned Scale = MI->getOperand(2).getImmedValue();
unsigned R2 = MI->getOperand(3).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
unsigned Offset = MI->getOperand(4).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
BuildMI(Opcode, 5, R0).addReg(R1).addZImm(Scale).
addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
@ -146,6 +146,31 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
case X86::XORri32: Opcode = X86::XORri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned Scale = MI->getOperand(1).getImmedValue();
unsigned R1 = MI->getOperand(2).getReg();
unsigned Offset = MI->getOperand(3).getImmedValue();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 5).addReg(R0).addZImm(Scale).
addReg(R1).addSImm(Offset).addZImm((char)Val));
return true;
}
}
return false;
case X86::ANDmi16: case X86::ANDmi32:
assert(MI->getNumOperands() == 5 && "These should all have 5 operands!");
if (MI->getOperand(4).isImmediate()) {
int Val = MI->getOperand(4).getImmedValue();
// If the value is the same when signed extended from 8 bits...
if (Val == (signed int)(signed char)Val) {
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
case X86::ANDmi16: Opcode = X86::ANDmi16b; break;
case X86::ANDmi32: Opcode = X86::ANDmi32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val));
return true;