Expand pseudos/macros for Selt. This is the last of the complex

macros.The rest is some small misc. stuff.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2013-02-23 03:09:56 +00:00
parent 1e8ed2537b
commit 50354a3f4a
5 changed files with 93 additions and 10 deletions

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@ -416,6 +416,7 @@ class SelT<string op1, string op2>:
!strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> { !strconcat(op1, "\t.+4\n\tmove $rd, $rs"))), []> {
let isCodeGenOnly=1; let isCodeGenOnly=1;
let Constraints = "$rd = $rd_"; let Constraints = "$rd = $rd_";
let usesCustomInserter = 1;
} }
// //

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@ -1298,6 +1298,72 @@ MachineBasicBlock *MipsTargetLowering::EmitSel16(unsigned Opc, MachineInstr *MI,
return BB; return BB;
} }
MachineBasicBlock *MipsTargetLowering::EmitSelT16
(unsigned Opc1, unsigned Opc2,
MachineInstr *MI, MachineBasicBlock *BB) const {
if (DontExpandCondPseudos16)
return BB;
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
DebugLoc dl = MI->getDebugLoc();
// To "insert" a SELECT_CC instruction, we actually have to insert the
// diamond control-flow pattern. The incoming instruction knows the
// destination vreg to set, the condition code register to branch on, the
// true/false values to select between, and a branch opcode to use.
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineFunction::iterator It = BB;
++It;
// thisMBB:
// ...
// TrueVal = ...
// setcc r1, r2, r3
// bNE r1, r0, copy1MBB
// fallthrough --> copy0MBB
MachineBasicBlock *thisMBB = BB;
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
// Transfer the remainder of BB and its successor edges to sinkMBB.
sinkMBB->splice(sinkMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);
BuildMI(BB, dl, TII->get(Opc2)).addReg(MI->getOperand(3).getReg())
.addReg(MI->getOperand(4).getReg());
BuildMI(BB, dl, TII->get(Opc1)).addMBB(sinkMBB);
// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
BB = copy0MBB;
// Update machine-CFG edges
BB->addSuccessor(sinkMBB);
// sinkMBB:
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
// ...
BB = sinkMBB;
BuildMI(*BB, BB->begin(), dl,
TII->get(Mips::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB)
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB);
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
MachineBasicBlock *MipsTargetLowering::EmitSeliT16 MachineBasicBlock *MipsTargetLowering::EmitSeliT16
(unsigned Opc1, unsigned Opc2, (unsigned Opc1, unsigned Opc2,
MachineInstr *MI, MachineBasicBlock *BB) const { MachineInstr *MI, MachineBasicBlock *BB) const {
@ -1490,6 +1556,18 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB); return EmitSeliT16(Mips::BtnezX16, Mips::SltiRxImmX16, MI, BB);
case Mips::SelTBtneZSltiu: case Mips::SelTBtneZSltiu:
return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB); return EmitSeliT16(Mips::BtnezX16, Mips::SltiuRxImmX16, MI, BB);
case Mips::SelTBteqZCmp:
return EmitSelT16(Mips::BteqzX16, Mips::CmpRxRy16, MI, BB);
case Mips::SelTBteqZSlt:
return EmitSelT16(Mips::BteqzX16, Mips::SltRxRy16, MI, BB);
case Mips::SelTBteqZSltu:
return EmitSelT16(Mips::BteqzX16, Mips::SltuRxRy16, MI, BB);
case Mips::SelTBtneZCmp:
return EmitSelT16(Mips::BtnezX16, Mips::CmpRxRy16, MI, BB);
case Mips::SelTBtneZSlt:
return EmitSelT16(Mips::BtnezX16, Mips::SltRxRy16, MI, BB);
case Mips::SelTBtneZSltu:
return EmitSelT16(Mips::BtnezX16, Mips::SltuRxRy16, MI, BB);
} }
} }

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@ -410,6 +410,9 @@ namespace llvm {
MachineInstr *MI, MachineInstr *MI,
MachineBasicBlock *BB) const; MachineBasicBlock *BB) const;
MachineBasicBlock *EmitSelT16(unsigned Opc1, unsigned Opc2,
MachineInstr *MI,
MachineBasicBlock *BB) const;
}; };
} }

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@ -15,3 +15,4 @@ bosco: ; preds = %bosco, %entry
; CHECK-STATIC: j $BB0_1 ; CHECK-STATIC: j $BB0_1
; CHECK-PIC16: b $BB0_1 ; CHECK-PIC16: b $BB0_1
; CHECK-STATIC16: b $BB0_1 ; CHECK-STATIC16: b $BB0_1

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@ -20,7 +20,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
; 16: bteqz .+4 ; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
store i32 %cond, i32* @z2, align 4 store i32 %cond, i32* @z2, align 4
%4 = load i32* @c, align 4 %4 = load i32* @c, align 4
@ -91,7 +91,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}} ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: bteqz .+4 ; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp sge i32 %1, %0 %cmp1 = icmp sge i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2 %cond5 = select i1 %cmp1, i32 %3, i32 %2
@ -112,7 +112,7 @@ entry:
%1 = load i32* @b, align 4 %1 = load i32* @b, align 4
%cmp = icmp sgt i32 %0, %1 %cmp = icmp sgt i32 %0, %1
; 16: slt ${{[0-9]+}}, ${{[0-9]+}} ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: btnez .+4 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%2 = load i32* @f, align 4 %2 = load i32* @f, align 4
%3 = load i32* @t, align 4 %3 = load i32* @t, align 4
@ -141,7 +141,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: slt ${{[0-9]+}}, ${{[0-9]+}} ; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
; 16: bteqz .+4 ; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp sle i32 %1, %0 %cmp1 = icmp sle i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2 %cond5 = select i1 %cmp1, i32 %3, i32 %2
@ -165,7 +165,7 @@ entry:
%cond = select i1 %cmp, i32 %1, i32 %2 %cond = select i1 %cmp, i32 %1, i32 %2
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: slti ${{[0-9]+}}, {{[0-9]+}} ; 16: slti ${{[0-9]+}}, {{[0-9]+}}
; 16: btnez .+4 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%3 = load i32* @b, align 4 %3 = load i32* @b, align 4
%cmp1 = icmp slt i32 %3, 2 %cmp1 = icmp slt i32 %3, 2
@ -192,7 +192,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}} ; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
; 16: btnez .+4 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
store i32 %cond, i32* @z2, align 4 store i32 %cond, i32* @z2, align 4
%4 = load i32* @c, align 4 %4 = load i32* @c, align 4
@ -284,7 +284,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: bteqz .+4 ; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp uge i32 %1, %0 %cmp1 = icmp uge i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2 %cond5 = select i1 %cmp1, i32 %3, i32 %2
@ -309,7 +309,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: btnez .+4 ; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp ugt i32 %1, %0 %cmp1 = icmp ugt i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2 %cond5 = select i1 %cmp1, i32 %3, i32 %2
@ -334,7 +334,7 @@ entry:
%cond = select i1 %cmp, i32 %2, i32 %3 %cond = select i1 %cmp, i32 %2, i32 %3
store i32 %cond, i32* @z1, align 4 store i32 %cond, i32* @z1, align 4
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}} ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
; 16: bteqz .+4 ; 16: bteqz $BB{{[0-9]+}}_{{[0-9]}}
; 16: move ${{[0-9]+}}, ${{[0-9]+}} ; 16: move ${{[0-9]+}}, ${{[0-9]+}}
%cmp1 = icmp ule i32 %1, %0 %cmp1 = icmp ule i32 %1, %0
%cond5 = select i1 %cmp1, i32 %3, i32 %2 %cond5 = select i1 %cmp1, i32 %3, i32 %2