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80-col fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121356 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -669,7 +669,8 @@ SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
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if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
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EVT MemVT = LD->getMemoryVT();
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EVT MemVT = LD->getMemoryVT();
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ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
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ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
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? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
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? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
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: ISD::EXTLOAD)
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: LD->getExtensionType();
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: LD->getExtensionType();
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Replace = true;
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Replace = true;
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return DAG.getExtLoad(ExtType, PVT, dl,
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return DAG.getExtLoad(ExtType, PVT, dl,
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@ -892,7 +893,8 @@ bool DAGCombiner::PromoteLoad(SDValue Op) {
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LoadSDNode *LD = cast<LoadSDNode>(N);
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LoadSDNode *LD = cast<LoadSDNode>(N);
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EVT MemVT = LD->getMemoryVT();
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EVT MemVT = LD->getMemoryVT();
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ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
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ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
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? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD : ISD::EXTLOAD)
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? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
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: ISD::EXTLOAD)
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: LD->getExtensionType();
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: LD->getExtensionType();
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SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
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SDValue NewLD = DAG.getExtLoad(ExtType, PVT, dl,
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LD->getChain(), LD->getBasePtr(),
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LD->getChain(), LD->getBasePtr(),
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@ -2826,7 +2828,8 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
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LHS->getOperand(1), N->getOperand(1));
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LHS->getOperand(1), N->getOperand(1));
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// Create the new shift.
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// Create the new shift.
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SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
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SDValue NewShift = DAG.getNode(N->getOpcode(),
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LHS->getOperand(0).getDebugLoc(),
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VT, LHS->getOperand(0), N->getOperand(1));
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VT, LHS->getOperand(0), N->getOperand(1));
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// Create the new binop.
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// Create the new binop.
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@ -2989,7 +2992,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) {
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if (N01C && N1C) {
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if (N01C && N1C) {
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// Determine what the truncate's result bitsize and type would be.
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// Determine what the truncate's result bitsize and type would be.
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EVT TruncVT =
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EVT TruncVT =
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EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
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EVT::getIntegerVT(*DAG.getContext(),
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OpSizeInBits - N1C->getZExtValue());
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// Determine the residual right-shift amount.
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// Determine the residual right-shift amount.
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signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
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signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
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@ -6252,7 +6256,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
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// Check the resultant load doesn't need a higher alignment than the
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// Check the resultant load doesn't need a higher alignment than the
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// original load.
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// original load.
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unsigned NewAlign =
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unsigned NewAlign =
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TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
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TLI.getTargetData()
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->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
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if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
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if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
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return SDValue();
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return SDValue();
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@ -7053,7 +7058,8 @@ SDValue DAGCombiner::BuildUDIV(SDNode *N) {
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}
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}
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/// FindBaseOffset - Return true if base is a frame index, which is known not
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/// FindBaseOffset - Return true if base is a frame index, which is known not
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// to alias with anything but itself. Provides base object and offset as results.
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// to alias with anything but itself. Provides base object and offset as
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// results.
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static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
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static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
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const GlobalValue *&GV, void *&CV) {
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const GlobalValue *&GV, void *&CV) {
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// Assume it is a primitive operation.
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// Assume it is a primitive operation.
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