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Pseudo CMOV instructions don't clobber EFLAGS.

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The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139057 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-09-02 23:52:55 +00:00
parent b8e052e123
commit 5047d76575
3 changed files with 9 additions and 19 deletions
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16
lib/Target/X86/X86InstrCompiler.td
View File

@ -349,18 +349,11 @@ def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
//===----------------------------------------------------------------------===//
// Conditional Move Pseudo Instructions
let Constraints = "$src1 = $dst" in {
// Conditional moves
let Uses = [EFLAGS] in {
// X86 doesn't have 8-bit conditional moves. Use a customInserter to
// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
// however that requires promoting the operands, and can induce additional
// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
// clobber EFLAGS, because if one of the operands is zero, the expansion
// could involve an xor.
let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
// i8 register pressure.
let usesCustomInserter = 1, Uses = [EFLAGS] in {
def CMOV_GR8 : I<0, Pseudo,
(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
"#CMOV_GR8 PSEUDO!",
@ -400,10 +393,7 @@ def CMOV_RFP80 : I<0, Pseudo,
(X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
EFLAGS))]>;
} // Predicates = [NoCMov]
} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
} // Uses = [EFLAGS]
} // Constraints = "$src1 = $dst" in
} // UsesCustomInserter = 1, Uses = [EFLAGS]
//===----------------------------------------------------------------------===//

4
test/CodeGen/X86/cmov.ll
View File

@ -90,8 +90,8 @@ bb.i.i.i: ; preds = %entry
; CHECK: test4:
; CHECK: g_100
; CHECK: testb
; CHECK: testb %al, %al
; CHECK-NEXT: setne %al
; CHECK-NOT: xor
; CHECK: setne
; CHECK-NEXT: testb
func_4.exit.i: ; preds = %bb.i.i.i, %entry

8
test/CodeGen/X86/or-address.ll
View File

@ -47,10 +47,10 @@ return: ; preds = %bb
}
; CHECK: test1:
; CHECK: movl %{{.*}}, (%rdi,%rcx,4)
; CHECK: movl %{{.*}}, 8(%rdi,%rcx,4)
; CHECK: movl %{{.*}}, 4(%rdi,%rcx,4)
; CHECK: movl %{{.*}}, 12(%rdi,%rcx,4)
; CHECK: movl %{{.*}}, (%[[RDI:...]],%[[RCX:...]],4)
; CHECK: movl %{{.*}}, 8(%[[RDI]],%[[RCX]],4)
; CHECK: movl %{{.*}}, 4(%[[RDI]],%[[RCX]],4)
; CHECK: movl %{{.*}}, 12(%[[RDI]],%[[RCX]],4)
define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind {
bb.nph: