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[Hexagon] Adding tstbit/bitclr/bitset instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224374 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2014-12-16 21:28:58 +00:00
parent 95aa8cab27
commit 504c77f9c8
2 changed files with 111 additions and 24 deletions
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125
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -2947,6 +2947,107 @@ def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
(S2_togglebit_r IntRegs:$Rs, IntRegs:$Rt)>;
// Bit test
let hasSideEffects = 0 in
class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
"$Pd = "#MnOp#"($Rs, #$u5)",
[], "", S_2op_tc_2early_SLOT23> {
bits<2> Pd;
bits<5> Rs;
bits<5> u5;
let IClass = 0b1000;
let Inst{27-24} = 0b0101;
let Inst{23-21} = MajOp;
let Inst{20-16} = Rs;
let Inst{13} = 0;
let Inst{12-8} = u5;
let Inst{1-0} = Pd;
}
let hasSideEffects = 0 in
class T_TEST_BIT_REG<string MnOp, bit IsNeg>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
"$Pd = "#MnOp#"($Rs, $Rt)",
[], "", S_3op_tc_2early_SLOT23> {
bits<2> Pd;
bits<5> Rs;
bits<5> Rt;
let IClass = 0b1100;
let Inst{27-22} = 0b011100;
let Inst{21} = IsNeg;
let Inst{20-16} = Rs;
let Inst{12-8} = Rt;
let Inst{1-0} = Pd;
}
let isCodeGenOnly = 0 in {
def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
}
let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
(S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
(S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
(S2_tstbit_i IntRegs:$Rs, 0)>;
def: Pat<(i1 (trunc (i64 DoubleRegs:$Rs))),
(S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>;
}
let hasSideEffects = 0 in
class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
"$Pd = "#MnOp#"($Rs, #$u6)",
[], "", S_2op_tc_2early_SLOT23> {
bits<2> Pd;
bits<5> Rs;
bits<6> u6;
let IClass = 0b1000;
let Inst{27-24} = 0b0101;
let Inst{23-22} = MajOp;
let Inst{21} = IsNeg;
let Inst{20-16} = Rs;
let Inst{13-8} = u6;
let Inst{1-0} = Pd;
}
let hasSideEffects = 0 in
class T_TEST_BITS_REG<string MnOp, bits<2> MajOp, bit IsNeg>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
"$Pd = "#MnOp#"($Rs, $Rt)",
[], "", S_3op_tc_2early_SLOT23> {
bits<2> Pd;
bits<5> Rs;
bits<5> Rt;
let IClass = 0b1100;
let Inst{27-24} = 0b0111;
let Inst{23-22} = MajOp;
let Inst{21} = IsNeg;
let Inst{20-16} = Rs;
let Inst{12-8} = Rt;
let Inst{1-0} = Pd;
}
let isCodeGenOnly = 0 in {
def C2_bitsclri : T_TEST_BITS_IMM<"bitsclr", 0b10, 0>;
def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
}
let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
(C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
(C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
}
let AddedComplexity = 10 in // Complexity greater than compare reg-reg.
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), IntRegs:$Rt)),
(C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
// clrbit.
def CLRBIT : ALU64_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
"$dst = clrbit($src1, #$src2)",
@ -3025,30 +3126,6 @@ def C2_tfrrp: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs),
let Inst{1-0} = Pd;
}
let hasSideEffects = 0 in
class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
"$Pd = "#MnOp#"($Rs, #$u5)",
[], "", S_2op_tc_2early_SLOT23> {
bits<2> Pd;
bits<5> Rs;
bits<5> u5;
let IClass = 0b1000;
let Inst{27-24} = 0b0101;
let Inst{23-21} = MajOp;
let Inst{20-16} = Rs;
let Inst{13} = 0;
let Inst{12-8} = u5;
let Inst{1-0} = Pd;
}
def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
(S2_tstbit_i IntRegs:$Rs, 0)>;
}
//===----------------------------------------------------------------------===//
// STYPE/PRED -

10
test/MC/Disassembler/Hexagon/xtype_pred.txt
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@ -6,11 +6,21 @@
# CHECK: p3 = cmp.gt(r21:20, r31:30)
0x83 0xde 0x94 0xd2
# CHECK: p3 = cmp.gtu(r21:20, r31:30)
0x03 0xd5 0x91 0x85
# CHECK: p3 = bitsclr(r17, #21)
0x03 0xd5 0x51 0xc7
# CHECK: p3 = bitsset(r17, r21)
0x03 0xd5 0x91 0xc7
# CHECK: p3 = bitsclr(r17, r21)
0x10 0xc3 0x00 0x86
# CHECK: r17:16 = mask(p3)
0x03 0xc0 0x45 0x85
# CHECK: p3 = r5
0x05 0xc0 0x43 0x89
# CHECK: r5 = p3
0x03 0xd5 0x11 0x85
# CHECK: p3 = tstbit(r17, #21)
0x03 0xd5 0x11 0xc7
# CHECK: p3 = tstbit(r17, r21)
0x11 0xc2 0x03 0x89
# CHECK: r17 = vitpack(p3, p2)