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Relax the checking on zextload generation a bit, since as sabre pointed out
you could be AND'ing with the result of a shift that shifts out all the bits you care about, in addition to a constant. Also, move over an add/sub_parts fold from legalize to the dag combiner, where it works for things other than constants. Woot! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23720 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -147,11 +147,13 @@ namespace {
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SDOperand visitSELECT(SDNode *N);
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SDOperand visitSELECT_CC(SDNode *N);
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SDOperand visitSETCC(SDNode *N);
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SDOperand visitADD_PARTS(SDNode *N);
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SDOperand visitSUB_PARTS(SDNode *N);
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SDOperand visitSIGN_EXTEND(SDNode *N);
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SDOperand visitZERO_EXTEND(SDNode *N);
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SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
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SDOperand visitTRUNCATE(SDNode *N);
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SDOperand visitFADD(SDNode *N);
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SDOperand visitFSUB(SDNode *N);
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SDOperand visitFMUL(SDNode *N);
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@ -422,6 +424,8 @@ SDOperand DAGCombiner::visit(SDNode *N) {
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case ISD::SELECT: return visitSELECT(N);
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case ISD::SELECT_CC: return visitSELECT_CC(N);
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case ISD::SETCC: return visitSETCC(N);
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case ISD::ADD_PARTS: return visitADD_PARTS(N);
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case ISD::SUB_PARTS: return visitSUB_PARTS(N);
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case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
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case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
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case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
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@ -800,11 +804,11 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
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}
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// fold (zext_inreg (extload x)) -> (zextload x)
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if (N1C && N0.getOpcode() == ISD::EXTLOAD) {
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if (N0.getOpcode() == ISD::EXTLOAD) {
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MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
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// If we zero all the possible extended bits, then we can turn this into
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// a zextload if we are running before legalize or the operation is legal.
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if (MaskedValueIsZero(SDOperand(N,0), ~0ULL<<MVT::getSizeInBits(EVT),TLI) &&
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if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
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(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
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SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
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N0.getOperand(1), N0.getOperand(2),
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@ -815,11 +819,11 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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}
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}
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// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
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if (N1C && N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) {
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if (N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) {
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MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
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// If we zero all the possible extended bits, then we can turn this into
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// a zextload if we are running before legalize or the operation is legal.
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if (MaskedValueIsZero(SDOperand(N,0), ~0ULL<<MVT::getSizeInBits(EVT),TLI) &&
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if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
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(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
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SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
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N0.getOperand(1), N0.getOperand(2),
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@ -1230,6 +1234,46 @@ SDOperand DAGCombiner::visitSETCC(SDNode *N) {
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cast<CondCodeSDNode>(N->getOperand(2))->get());
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}
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SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
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SDOperand LHSLo = N->getOperand(0);
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SDOperand RHSLo = N->getOperand(2);
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MVT::ValueType VT = LHSLo.getValueType();
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// fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
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if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
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SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
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N->getOperand(3));
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WorkList.push_back(Hi.Val);
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CombineTo(N, RHSLo, Hi);
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return SDOperand();
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}
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// fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
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if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
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SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
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N->getOperand(3));
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WorkList.push_back(Hi.Val);
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CombineTo(N, LHSLo, Hi);
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return SDOperand();
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}
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return SDOperand();
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}
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SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
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SDOperand LHSLo = N->getOperand(0);
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SDOperand RHSLo = N->getOperand(2);
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MVT::ValueType VT = LHSLo.getValueType();
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// fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
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if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
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SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
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N->getOperand(3));
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WorkList.push_back(Hi.Val);
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CombineTo(N, LHSLo, Hi);
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return SDOperand();
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}
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return SDOperand();
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}
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SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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SDOperand N0 = N->getOperand(0);
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ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
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@ -2449,33 +2449,11 @@ ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
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ExpandOp(LHS, LHSL, LHSH);
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ExpandOp(RHS, RHSL, RHSH);
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// FIXME: this should be moved to the dag combiner someday.
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assert(NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS);
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if (LHSL.getValueType() == MVT::i32) {
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SDOperand LowEl = SDOperand(0,0);
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
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if (C->getValue() == 0)
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LowEl = RHSL;
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
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if (C->getValue() == 0)
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LowEl = LHSL;
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if (LowEl.Val) {
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// Turn this into an add/sub of the high part only.
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SDOperand HiEl =
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DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
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LowEl.getValueType(), LHSH, RHSH);
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Lo = LowEl;
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Hi = HiEl;
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return;
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}
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}
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std::vector<SDOperand> Ops;
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Ops.push_back(LHSL);
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Ops.push_back(LHSH);
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Ops.push_back(RHSL);
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Ops.push_back(RHSH);
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std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
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Lo = DAG.getNode(NodeOp, VTs, Ops);
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Hi = Lo.getValue(1);
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