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RangeIsDefinedByCopyFromReg() should check for subreg_to_reg, insert_subreg,
and extract_subreg as a "copy" that defines a valno. Also fixes a typo. These two issues prevent a simple subreg coalescing from happening before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86022 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1369,7 +1369,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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if (SrcSubIdx)
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SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
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assert(SrcSubRC && "Illegal subregister index");
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if (!SrcSubRC->contains(DstReg)) {
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if (!SrcSubRC->contains(DstSubReg)) {
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DEBUG(errs() << "\tIncompatible source regclass: "
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<< tri_->getName(DstSubReg) << " not in "
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<< SrcSubRC->getName() << ".\n");
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@ -1834,6 +1834,25 @@ static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
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return std::find(V.begin(), V.end(), Val) != V.end();
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}
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static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
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const TargetInstrInfo *TII,
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const TargetRegisterInfo *TRI) {
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
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;
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else if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
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DstReg = MI->getOperand(0).getReg();
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SrcReg = MI->getOperand(1).getReg();
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} else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
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MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
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DstReg = MI->getOperand(0).getReg();
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SrcReg = MI->getOperand(2).getReg();
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} else
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return false;
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return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
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(DstReg == DR || TRI->isSuperRegister(DR, DstReg));
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}
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/// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
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/// the specified live interval is defined by a copy from the specified
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/// register.
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@ -1850,12 +1869,9 @@ bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
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// It's a sub-register live interval, we may not have precise information.
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// Re-compute it.
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MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (DefMI &&
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tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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DstReg == li.reg && SrcReg == Reg) {
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if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
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// Cache computed info.
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LR->valno->def = LR->start;
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LR->valno->def = LR->start;
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LR->valno->setCopy(DefMI);
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return true;
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}
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15
test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
Normal file
15
test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
Normal file
@ -0,0 +1,15 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin11 | FileCheck %s
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; rdar://7362871
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define void @bar(i32 %b, i32 %a) nounwind optsize ssp {
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entry:
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; CHECK: leal 15(%rsi), %edi
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; CHECK-NOT: movl
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; CHECK: call _foo
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%0 = add i32 %a, 15 ; <i32> [#uses=1]
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%1 = zext i32 %0 to i64 ; <i64> [#uses=1]
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tail call void @foo(i64 %1) nounwind
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ret void
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}
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declare void @foo(i64)
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