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R600/SI: Move finding SGPR operand to move to separate function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218533 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1389,72 +1389,10 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
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// XXX - Do any VOP3 instructions read VCC?
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// XXX - Do any VOP3 instructions read VCC?
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// Legalize VOP3
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// Legalize VOP3
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if (isVOP3(MI->getOpcode())) {
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if (isVOP3(MI->getOpcode())) {
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const MCInstrDesc &Desc = get(MI->getOpcode());
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int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
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int VOP3Idx[3] = { Src0Idx, Src1Idx, Src2Idx };
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// Find the one SGPR operand we are allowed to use.
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// Find the one SGPR operand we are allowed to use.
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unsigned SGPRReg = AMDGPU::NoRegister;
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unsigned SGPRReg = findUsedSGPR(MI, VOP3Idx);
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for (const MachineOperand &MO : MI->implicit_operands()) {
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// We only care about reads.
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if (MO.isDef())
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continue;
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if (MO.getReg() == AMDGPU::VCC) {
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SGPRReg = AMDGPU::VCC;
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break;
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}
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if (MO.getReg() == AMDGPU::FLAT_SCR) {
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SGPRReg = AMDGPU::FLAT_SCR;
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break;
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}
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}
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if (SGPRReg == AMDGPU::NoRegister) {
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unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
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// First we need to consider the instruction's operand requirements before
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// legalizing. Some operands are required to be SGPRs, but we are still
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// bound by the constant bus requirement to only use one.
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//
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// If the operand's class is an SGPR, we can never move it.
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for (unsigned i = 0; i < 3; ++i) {
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int Idx = VOP3Idx[i];
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if (Idx == -1)
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break;
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const MachineOperand &MO = MI->getOperand(Idx);
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if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
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SGPRReg = MO.getReg();
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if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
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UsedSGPRs[i] = MO.getReg();
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}
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if (SGPRReg == AMDGPU::NoRegister) {
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// We don't have a required SGPR operand, so we have a bit more freedom in
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// selecting operands to move.
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// Try to select the most used SGPR. If an SGPR is equal to one of the
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// others, we choose that.
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//
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// e.g.
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// V_FMA_F32 v0, s0, s0, s0 -> No moves
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// V_FMA_F32 v0, s0, s1, s0 -> Move s1
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if (UsedSGPRs[0] != AMDGPU::NoRegister) {
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if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
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SGPRReg = UsedSGPRs[0];
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}
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if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
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if (UsedSGPRs[1] == UsedSGPRs[2])
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SGPRReg = UsedSGPRs[1];
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}
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}
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}
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for (unsigned i = 0; i < 3; ++i) {
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for (unsigned i = 0; i < 3; ++i) {
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int Idx = VOP3Idx[i];
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int Idx = VOP3Idx[i];
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@ -2215,6 +2153,74 @@ void SIInstrInfo::addDescImplicitUseDef(const MCInstrDesc &NewDesc,
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}
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}
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}
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}
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unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
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int OpIndices[3]) const {
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const MCInstrDesc &Desc = get(MI->getOpcode());
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// Find the one SGPR operand we are allowed to use.
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unsigned SGPRReg = AMDGPU::NoRegister;
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// First we need to consider the instruction's operand requirements before
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// legalizing. Some operands are required to be SGPRs, such as implicit uses
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// of VCC, but we are still bound by the constant bus requirement to only use
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// one.
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//
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// If the operand's class is an SGPR, we can never move it.
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for (const MachineOperand &MO : MI->implicit_operands()) {
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// We only care about reads.
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if (MO.isDef())
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continue;
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if (MO.getReg() == AMDGPU::VCC)
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return AMDGPU::VCC;
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if (MO.getReg() == AMDGPU::FLAT_SCR)
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return AMDGPU::FLAT_SCR;
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}
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unsigned UsedSGPRs[3] = { AMDGPU::NoRegister };
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const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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for (unsigned i = 0; i < 3; ++i) {
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int Idx = OpIndices[i];
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if (Idx == -1)
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break;
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const MachineOperand &MO = MI->getOperand(Idx);
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if (RI.isSGPRClassID(Desc.OpInfo[Idx].RegClass))
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SGPRReg = MO.getReg();
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if (MO.isReg() && RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
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UsedSGPRs[i] = MO.getReg();
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}
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if (SGPRReg != AMDGPU::NoRegister)
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return SGPRReg;
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// We don't have a required SGPR operand, so we have a bit more freedom in
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// selecting operands to move.
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// Try to select the most used SGPR. If an SGPR is equal to one of the
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// others, we choose that.
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//
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// e.g.
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// V_FMA_F32 v0, s0, s0, s0 -> No moves
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// V_FMA_F32 v0, s0, s1, s0 -> Move s1
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if (UsedSGPRs[0] != AMDGPU::NoRegister) {
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if (UsedSGPRs[0] == UsedSGPRs[1] || UsedSGPRs[0] == UsedSGPRs[2])
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SGPRReg = UsedSGPRs[0];
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}
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if (SGPRReg == AMDGPU::NoRegister && UsedSGPRs[1] != AMDGPU::NoRegister) {
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if (UsedSGPRs[1] == UsedSGPRs[2])
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SGPRReg = UsedSGPRs[1];
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}
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return SGPRReg;
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}
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MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
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MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
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MachineBasicBlock *MBB,
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MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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@ -55,6 +55,8 @@ private:
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void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
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void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const;
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unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const;
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public:
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public:
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explicit SIInstrInfo(const AMDGPUSubtarget &st);
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explicit SIInstrInfo(const AMDGPUSubtarget &st);
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