From 508e1d3db536b736063385eb1f885b446a1385ca Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Thu, 11 Aug 2011 20:47:56 +0000 Subject: [PATCH] Fix decoding for indexed STRB and LDRB. Fixes . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137347 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 4 ++++ test/MC/Disassembler/ARM/arm-tests.txt | 3 +++ 2 files changed, 7 insertions(+) diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 8cfb21793e9..d2809f0c2c9 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -941,6 +941,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::STR_POST_IMM: case ARM::STR_POST_REG: + case ARM::STRB_POST_IMM: + case ARM::STRB_POST_REG: case ARM::STRTr: case ARM::STRTi: case ARM::STRBT_POST_REG: @@ -957,6 +959,8 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, switch (Inst.getOpcode()) { case ARM::LDR_POST_IMM: case ARM::LDR_POST_REG: + case ARM::LDRB_POST_IMM: + case ARM::LDRB_POST_REG: case ARM::LDR_PRE: case ARM::LDRBT_POST_REG: case ARM::LDRBT_POST_IMM: diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index a6299895f99..c306a0656b0 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -305,3 +305,6 @@ # CHECK: andeq r0, r0, r0, lsr #32 0x20 0x00 0x00 0x00 + +# CHECK: strb r3, [r2], #1 +0x01 0x30 0xc2 0xe4