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Add libm-oriented ISD opcodes for rounding operations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55130 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-08-21 17:55:02 +00:00
parent f93cf79505
commit 509e84fa71
5 changed files with 29 additions and 3 deletions
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7
include/llvm/CodeGen/SelectionDAGNodes.h
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@ -423,10 +423,11 @@ namespace ISD {
// conversions, but that is a noop, deleted by getNode().
BIT_CONVERT,
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW - Perform unary floating point
// negation, absolute value, square root, sine and cosine, powi, and pow
// operations.
// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
// FCEIL, FTRUNC, FRINT, FNEARYINT, FFLOOR - Perform various unary floating
// point operations. These are inspired by libm.
FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR,
// LOAD and STORE have token chains as their first operand, then the same
// operands as an LLVM load/store instruction, then an offset node that

5
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3493,6 +3493,11 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
case ISD::FRINT:
case ISD::FNEARBYINT:
Tmp1 = LegalizeOp(Node->getOperand(0));
switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
case TargetLowering::Promote:

10
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -61,6 +61,11 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FP_TO_UINT:
case ISD::FSIN:
case ISD::FSQRT:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
case ISD::FRINT:
case ISD::FNEARBYINT:
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
@ -298,6 +303,11 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::FSQRT:
case ISD::FSIN:
case ISD::FCOS:
case ISD::FTRUNC:
case ISD::FFLOOR:
case ISD::FCEIL:
case ISD::FRINT:
case ISD::FNEARBYINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::SINT_TO_FP:

5
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -4771,6 +4771,11 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::FCOS: return "fcos";
case ISD::FPOWI: return "fpowi";
case ISD::FPOW: return "fpow";
case ISD::FTRUNC: return "ftrunc";
case ISD::FFLOOR: return "ffloor";
case ISD::FCEIL: return "fceil";
case ISD::FRINT: return "frint";
case ISD::FNEARBYINT: return "fnearbyint";
// Binary operators
case ISD::ADD: return "add";

5
lib/Target/TargetSelectionDAG.td
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@ -325,6 +325,11 @@ def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;