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Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
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test/MC/Disassembler/ARM/ldrd-armv4.txt
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test/MC/Disassembler/ARM/ldrd-armv4.txt
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@ -0,0 +1,15 @@
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# RUN: llvm-mc --disassemble %s -triple=armv4-linux-gnueabi |& FileCheck %s -check-prefix=V4
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# RUN: llvm-mc --disassemble %s -triple=armv5te-linux-gnueabi |& FileCheck %s -check-prefix=V5TE
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# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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# -------------------------------------------------------------------------------------------------
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# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X|
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# -------------------------------------------------------------------------------------------------
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#
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# A8.6.68 LDRD (register)
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# if Rt{0} = 1 then UNDEFINED;
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# V4: invalid instruction encoding
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# V5TE: ldrd
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0xd0 0x10 0x00 0x01
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