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Fix PR10656. It's only profitable to use 128-bit inserts and extracts

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when AVX mode is one. Otherwise is just more work for the type
legalizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137661 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-08-15 21:45:54 +00:00
parent 7a328270be
commit 50b37c7920
2 changed files with 26 additions and 4 deletions
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10
lib/Target/X86/X86ISelLowering.cpp
View File

@ -11737,7 +11737,8 @@ static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
/// PerformShuffleCombine - Performs several different shuffle combines.
static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI) {
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) {
DebugLoc dl = N->getDebugLoc();
EVT VT = N->getValueType(0);
@ -11746,8 +11747,9 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
return SDValue();
// Only handle pure VECTOR_SHUFFLE nodes.
if (VT.getSizeInBits() == 256 && N->getOpcode() == ISD::VECTOR_SHUFFLE)
// Combine 256-bit vector shuffles. This is only profitable when in AVX mode
if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
N->getOpcode() == ISD::VECTOR_SHUFFLE)
return PerformShuffleCombine256(N, DAG, DCI);
// Only handle 128 wide vector from here on.
@ -13220,7 +13222,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::VPERMILPD:
case X86ISD::VPERMILPDY:
case X86ISD::VPERM2F128:
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
}
return SDValue();

20
test/CodeGen/X86/avx-vinsertf128.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=CHECK-SSE %s
; CHECK-NOT: vunpck
; CHECK: vinsertf128 $1
@ -16,3 +17,22 @@ entry:
ret <4 x double> %shuffle
}
declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
; Just check that no crash happens
; CHECK-SSE: _insert_crash
define void @insert_crash() nounwind {
allocas:
%v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
%ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1>
%vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind
%ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind
%ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0
%double2float = fptrunc double %ret.i1.i.i464 to float
%smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3
%blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32>
store <4 x i32> %blendAsInt.i503, <4 x i32>* undef, align 4
ret void
}