From 50c3dfefd97ebd60ed6159728da644189865ae70 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Mon, 19 Jan 2009 08:19:57 +0000
Subject: [PATCH] Minor tweak to LowerUINT_TO_FP_i32. Bias (after
 scalar_to_vector) has two uses so we should make it the second source operand
 of ISD::OR so 2-address pass won't have to be smart about commuting.

%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>

The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62505 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelLowering.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 0f5103b5c67..c59e9cd7723 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4858,10 +4858,10 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
   SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64,
                            DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
                                        DAG.getNode(ISD::SCALAR_TO_VECTOR,
-                                                   MVT::v2f64, Bias)),
+                                                   MVT::v2f64, Load)),
                            DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
                                        DAG.getNode(ISD::SCALAR_TO_VECTOR,
-                                                   MVT::v2f64, Load)));
+                                                   MVT::v2f64, Bias)));
   Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
                    DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or),
                    DAG.getIntPtrConstant(0));