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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Modify the code that lowers shuffles to blends from using blendvXX to vblendXX.
blendv uses a register for the selection while vblend uses an immediate. On sandybridge they still have the same latency and execute on the same execution ports. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154396 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5391,59 +5391,76 @@ static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op,
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SDValue V1 = SVOp->getOperand(0);
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SDValue V2 = SVOp->getOperand(1);
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DebugLoc dl = SVOp->getDebugLoc();
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LLVMContext *Context = DAG.getContext();
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EVT VT = Op.getValueType();
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EVT InVT = V1.getValueType();
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EVT EltVT = VT.getVectorElementType();
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unsigned EltSize = EltVT.getSizeInBits();
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int MaskSize = VT.getVectorNumElements();
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int InSize = InVT.getVectorNumElements();
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// TODO: At the moment we only use AVX blends. We could also use SSE4 blends.
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if (!Subtarget->hasAVX())
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if (!Subtarget->hasSSE41())
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return SDValue();
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if (MaskSize != InSize)
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return SDValue();
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SmallVector<Constant*,2> MaskVals;
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ConstantInt *Zero = ConstantInt::get(*Context, APInt(EltSize, 0));
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ConstantInt *NegOne = ConstantInt::get(*Context, APInt(EltSize, -1));
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int ISDNo = 0;
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MVT OpTy;
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switch (VT.getSimpleVT().SimpleTy) {
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default: return SDValue();
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case MVT::v8i16:
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ISDNo = X86ISD::BLENDPW;
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OpTy = MVT::v8i16;
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break;
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case MVT::v4i32:
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case MVT::v4f32:
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ISDNo = X86ISD::BLENDPS;
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OpTy = MVT::v4f32;
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break;
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case MVT::v2i64:
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case MVT::v2f64:
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ISDNo = X86ISD::BLENDPD;
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OpTy = MVT::v2f64;
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break;
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case MVT::v8i32:
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case MVT::v8f32:
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if (!Subtarget->hasAVX())
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return SDValue();
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ISDNo = X86ISD::BLENDPS;
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OpTy = MVT::v8f32;
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break;
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case MVT::v4i64:
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case MVT::v4f64:
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if (!Subtarget->hasAVX())
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return SDValue();
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ISDNo = X86ISD::BLENDPD;
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OpTy = MVT::v4f64;
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break;
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case MVT::v16i16:
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if (!Subtarget->hasAVX2())
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return SDValue();
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ISDNo = X86ISD::BLENDPW;
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OpTy = MVT::v16i16;
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break;
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}
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assert(ISDNo && "Invalid Op Number");
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unsigned MaskVals = 0;
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for (int i = 0; i < MaskSize; ++i) {
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int EltIdx = SVOp->getMaskElt(i);
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if (EltIdx == i || EltIdx == -1)
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MaskVals.push_back(NegOne);
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MaskVals |= (1<<i);
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else if (EltIdx == (i + MaskSize))
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MaskVals.push_back(Zero);
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continue; // Bit is set to zero;
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else return SDValue();
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}
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Constant *MaskC = ConstantVector::get(MaskVals);
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EVT MaskTy = EVT::getEVT(MaskC->getType());
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assert(MaskTy.getSizeInBits() == VT.getSizeInBits() && "Invalid mask size");
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SDValue MaskIdx = DAG.getConstantPool(MaskC, PtrTy);
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unsigned Alignment = cast<ConstantPoolSDNode>(MaskIdx)->getAlignment();
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SDValue Mask = DAG.getLoad(MaskTy, dl, DAG.getEntryNode(), MaskIdx,
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MachinePointerInfo::getConstantPool(),
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false, false, false, Alignment);
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if (Subtarget->hasAVX2() && MaskTy == MVT::v32i8)
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return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2);
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if (Subtarget->hasAVX()) {
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switch (MaskTy.getSimpleVT().SimpleTy) {
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default: return SDValue();
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case MVT::v16i8:
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case MVT::v4i32:
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case MVT::v2i64:
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case MVT::v8i32:
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case MVT::v4i64:
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return DAG.getNode(ISD::VSELECT, dl, VT, Mask, V1, V2);
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}
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}
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return SDValue();
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V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
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V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
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SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
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DAG.getConstant(MaskVals, MVT::i32));
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return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
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}
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// v8i16 shuffles - Prefer shuffles in the following order:
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@ -11050,6 +11067,9 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::ANDNP: return "X86ISD::ANDNP";
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case X86ISD::PSIGN: return "X86ISD::PSIGN";
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case X86ISD::BLENDV: return "X86ISD::BLENDV";
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case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
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case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
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case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
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case X86ISD::HADD: return "X86ISD::HADD";
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case X86ISD::HSUB: return "X86ISD::HSUB";
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case X86ISD::FHADD: return "X86ISD::FHADD";
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@ -175,9 +175,14 @@ namespace llvm {
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/// PSIGN - Copy integer sign.
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PSIGN,
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/// BLEND family of opcodes
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/// BLENDV - Blend where the selector is an XMM.
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BLENDV,
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/// BLENDxx - Blend where the selector is an immediate.
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BLENDPW,
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BLENDPS,
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BLENDPD,
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/// HADD - Integer horizontal add.
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HADD,
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@ -126,6 +126,8 @@ def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<0,2>, SDTCisInt<3>]>;
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def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
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def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
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SDTCisSameAs<1,2>, SDTCisVT<3, i32>]>;
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def X86PAlign : SDNode<"X86ISD::PALIGN", SDTShuff3OpI>;
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@ -158,6 +160,10 @@ def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
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def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
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def X86Blendpw : SDNode<"X86ISD::BLENDPW", SDTBlend>;
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def X86Blendps : SDNode<"X86ISD::BLENDPS", SDTBlend>;
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def X86Blendpd : SDNode<"X86ISD::BLENDPD", SDTBlend>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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//===----------------------------------------------------------------------===//
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@ -6735,12 +6735,22 @@ let Predicates = [HasAVX] in {
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def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
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(v4f64 VR256:$src2))),
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(VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
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def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
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(imm:$mask))),
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(VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
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def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
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(imm:$mask))),
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(VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
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}
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let Predicates = [HasAVX2] in {
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def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
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(v32i8 VR256:$src2))),
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(VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
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def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
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(imm:$mask))),
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(VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
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}
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/// SS41I_ternary_int - SSE 4.1 ternary operator
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@ -6789,6 +6799,17 @@ let Predicates = [HasSSE41] in {
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def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
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(v2f64 VR128:$src2))),
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(BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
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def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
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(imm:$mask))),
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(VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
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def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
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(imm:$mask))),
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(VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
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def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
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(imm:$mask))),
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(VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
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}
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let Predicates = [HasAVX] in
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@ -164,7 +164,7 @@ i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32
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}
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; CHECK: blend1
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; CHECK: vblendvps
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; CHECK: vblendps
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; CHECK: ret
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define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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@ -172,7 +172,7 @@ define <4 x i32> @blend1(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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}
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; CHECK: blend2
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; CHECK: vblendvps
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; CHECK: vblendps
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; CHECK: ret
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define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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@ -180,7 +180,7 @@ define <4 x i32> @blend2(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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}
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; CHECK: blend2a
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; CHECK: vblendvps
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; CHECK: vblendps
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; CHECK: ret
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define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinline {
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%t = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
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@ -188,7 +188,7 @@ define <4 x float> @blend2a(<4 x float> %a, <4 x float> %b) nounwind alwaysinlin
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}
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; CHECK: blend3
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; CHECK-NOT: vblendvps
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; CHECK-NOT: vblendps
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; CHECK: ret
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define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 2, i32 7>
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@ -196,7 +196,7 @@ define <4 x i32> @blend3(<4 x i32> %a, <4 x i32> %b) nounwind alwaysinline {
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}
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; CHECK: blend4
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; CHECK: vblendvpd
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; CHECK: vblendpd
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; CHECK: ret
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define <4 x i64> @blend4(<4 x i64> %a, <4 x i64> %b) nounwind alwaysinline {
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%t = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
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@ -1,4 +1,4 @@
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; RUN: llc < %s -o /dev/null -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 3
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; RUN: llc < %s -o /dev/null -march=x86 -mattr=+sse2 -mtriple=i686-apple-darwin9 -stats -info-output-file - | grep asm-printer | grep 2
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define <4 x float> @func(<4 x float> %fp0, <4 x float> %fp1) nounwind {
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entry:
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