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Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
78d0835969
commit
50f1c37123
@ -3941,7 +3941,27 @@ def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
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def : t2InstAlias<"sxth${p} $Rd, $Rm",
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(t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
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(t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
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(t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
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(t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"uxtb${p} $Rd, $Rm",
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(t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"uxtb16${p} $Rd, $Rm",
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(t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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def : t2InstAlias<"uxth${p} $Rd, $Rm",
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(t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
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// Extend instruction w/o the ".w" optional width specifier.
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def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
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(t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot",
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(t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
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(t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
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(t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
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def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
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@ -3888,7 +3888,9 @@ processInstruction(MCInst &Inst,
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break;
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}
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case ARM::t2SXTH:
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case ARM::t2SXTB: {
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case ARM::t2SXTB:
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case ARM::t2UXTH:
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case ARM::t2UXTB: {
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// If we can use the 16-bit encoding and the user didn't explicitly
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// request the 32-bit variant, transform it here.
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if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
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@ -3896,8 +3898,14 @@ processInstruction(MCInst &Inst,
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Inst.getOperand(2).getImm() == 0 &&
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(!static_cast<ARMOperand*>(Operands[2])->isToken() ||
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static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
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unsigned NewOpc = (Inst.getOpcode() == ARM::t2SXTH) ?
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ARM::tSXTH : ARM::tSXTB;
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unsigned NewOpc;
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switch (Inst.getOpcode()) {
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default: llvm_unreachable("Illegal opcode!");
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case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
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case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
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case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
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case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
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}
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// The operands aren't the same for thumb1 (no rotate operand).
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MCInst TmpInst;
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TmpInst.setOpcode(NewOpc);
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@ -2946,3 +2946,121 @@ _func:
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@ CHECK: ite hi @ encoding: [0x8c,0xbf]
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@ CHECK: usub16hi r1, r1, r3 @ encoding: [0xd1,0xfa,0x43,0xf1]
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@ CHECK: usub8ls r9, r2, r3 @ encoding: [0xc2,0xfa,0x43,0xf9]
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@------------------------------------------------------------------------------
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@ UXTAB
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@------------------------------------------------------------------------------
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uxtab r2, r3, r4
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uxtab r4, r5, r6, ror #0
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it lt
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uxtablt r6, r2, r9, ror #8
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uxtab r5, r1, r4, ror #16
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uxtab r7, r8, r3, ror #24
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@ CHECK: uxtab r2, r3, r4 @ encoding: [0x53,0xfa,0x84,0xf2]
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@ CHECK: uxtab r4, r5, r6 @ encoding: [0x55,0xfa,0x86,0xf4]
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@ CHECK: it lt @ encoding: [0xb8,0xbf]
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@ CHECK: uxtablt r6, r2, r9, ror #8 @ encoding: [0x52,0xfa,0x99,0xf6]
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@ CHECK: uxtab r5, r1, r4, ror #16 @ encoding: [0x51,0xfa,0xa4,0xf5]
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@ CHECK: uxtab r7, r8, r3, ror #24 @ encoding: [0x58,0xfa,0xb3,0xf7]
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@------------------------------------------------------------------------------
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@ UXTAB16
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@------------------------------------------------------------------------------
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it ge
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uxtab16ge r0, r1, r4
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uxtab16 r6, r2, r7, ror #0
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uxtab16 r3, r5, r8, ror #8
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uxtab16 r3, r2, r1, ror #16
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it eq
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uxtab16eq r1, r2, r3, ror #24
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@ CHECK: it ge @ encoding: [0xa8,0xbf]
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@ CHECK: uxtab16ge r0, r1, r4 @ encoding: [0x31,0xfa,0x84,0xf0]
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@ CHECK: uxtab16 r6, r2, r7 @ encoding: [0x32,0xfa,0x87,0xf6]
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@ CHECK: uxtab16 r3, r5, r8, ror #8 @ encoding: [0x35,0xfa,0x98,0xf3]
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@ CHECK: uxtab16 r3, r2, r1, ror #16 @ encoding: [0x32,0xfa,0xa1,0xf3]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: uxtab16eq r1, r2, r3, ror #24 @ encoding: [0x32,0xfa,0xb3,0xf1]
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@------------------------------------------------------------------------------
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@ UXTAH
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@------------------------------------------------------------------------------
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uxtah r1, r3, r9
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it hi
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uxtahhi r6, r1, r6, ror #0
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uxtah r3, r8, r3, ror #8
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it lo
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uxtahlo r2, r2, r4, ror #16
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uxtah r9, r3, r3, ror #24
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@ CHECK: uxtah r1, r3, r9 @ encoding: [0x13,0xfa,0x89,0xf1]
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@ CHECK: it hi @ encoding: [0x88,0xbf]
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@ CHECK: uxtahhi r6, r1, r6 @ encoding: [0x11,0xfa,0x86,0xf6]
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@ CHECK: uxtah r3, r8, r3, ror #8 @ encoding: [0x18,0xfa,0x93,0xf3]
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@ CHECK: it lo @ encoding: [0x38,0xbf]
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@ CHECK: uxtahlo r2, r2, r4, ror #16 @ encoding: [0x12,0xfa,0xa4,0xf2]
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@ CHECK: uxtah r9, r3, r3, ror #24 @ encoding: [0x13,0xfa,0xb3,0xf9]
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@------------------------------------------------------------------------------
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@ UXTB
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@------------------------------------------------------------------------------
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it ge
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uxtbge r2, r4
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uxtb r5, r6, ror #0
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uxtb r6, r9, ror #8
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it cc
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uxtbcc r5, r1, ror #16
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uxtb r8, r3, ror #24
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@ CHECK: it ge @ encoding: [0xa8,0xbf]
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@ CHECK: uxtbge r2, r4 @ encoding: [0xe2,0xb2]
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@ CHECK: uxtb r5, r6 @ encoding: [0xf5,0xb2]
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@ CHECK: uxtb.w r6, r9, ror #8 @ encoding: [0x5f,0xfa,0x99,0xf6]
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@ CHECK: it lo @ encoding: [0x38,0xbf]
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@ CHECK: uxtblo.w r5, r1, ror #16 @ encoding: [0x5f,0xfa,0xa1,0xf5]
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@ CHECK: uxtb.w r8, r3, ror #24 @ encoding: [0x5f,0xfa,0xb3,0xf8]
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@------------------------------------------------------------------------------
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@ UXTB16
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@------------------------------------------------------------------------------
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uxtb16 r1, r4
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uxtb16 r6, r7, ror #0
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it cs
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uxtb16cs r3, r5, ror #8
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uxtb16 r3, r1, ror #16
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it ge
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uxtb16ge r2, r3, ror #24
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@ CHECK: uxtb16 r1, r4 @ encoding: [0x3f,0xfa,0x84,0xf1]
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@ CHECK: uxtb16 r6, r7 @ encoding: [0x3f,0xfa,0x87,0xf6]
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@ CHECK: it hs @ encoding: [0x28,0xbf]
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@ CHECK: uxtb16hs r3, r5, ror #8 @ encoding: [0x3f,0xfa,0x95,0xf3]
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@ CHECK: uxtb16 r3, r1, ror #16 @ encoding: [0x3f,0xfa,0xa1,0xf3]
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@ CHECK: it ge @ encoding: [0xa8,0xbf]
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@ CHECK: uxtb16ge r2, r3, ror #24 @ encoding: [0x3f,0xfa,0xb3,0xf2]
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@------------------------------------------------------------------------------
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@ UXTH
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@------------------------------------------------------------------------------
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it ne
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uxthne r3, r9
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uxth r1, r6, ror #0
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uxth r3, r8, ror #8
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it le
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uxthle r2, r2, ror #16
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uxth r9, r3, ror #24
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@ CHECK: it ne @ encoding: [0x18,0xbf]
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@ CHECK: uxthne.w r3, r9 @ encoding: [0x1f,0xfa,0x89,0xf3]
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@ CHECK: uxth r1, r6 @ encoding: [0xb1,0xb2]
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@ CHECK: uxth.w r3, r8, ror #8 @ encoding: [0x1f,0xfa,0x98,0xf3]
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@ CHECK: it le @ encoding: [0xd8,0xbf]
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@ CHECK: uxthle.w r2, r2, ror #16 @ encoding: [0x1f,0xfa,0xa2,0xf2]
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@ CHECK: uxth.w r9, r3, ror #24 @ encoding: [0x1f,0xfa,0xb3,0xf9]
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