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R600/SI: Move i64 -> v2i32 load promotion into AMDGPUDAGToDAGISel::Select()
We used to do this promotion during DAG legalization, but this caused an infinite loop in ExpandUnalignedLoad() because it assumed that i64 loads were legal if i64 was a legal type. It also seems better to report i64 loads as legal, since they actually are and we were just promoting them to simplify our tablegen files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226945 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -417,6 +417,28 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
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N->getValueType(0), Ops);
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}
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case ISD::LOAD: {
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// To simplify the TableGen patters, we replace all i64 loads with
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// v2i32 loads. Alternatively, we could promote i64 loads to v2i32
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// during DAG legalization, however, so places (ExpandUnalignedLoad)
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// in the DAG legalizer assume that if i64 is legal, so doing this
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// promotion early can cause problems.
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EVT VT = N->getValueType(0);
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LoadSDNode *LD = cast<LoadSDNode>(N);
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if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD)
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break;
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SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
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LD->getBasePtr(), LD->getMemOperand());
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SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
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MVT::i64, NewLoad);
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
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CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
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SelectCode(NewLoad.getNode());
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N = BitCast.getNode();
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break;
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}
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case AMDGPUISD::REGISTER_LOAD: {
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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break;
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@ -189,9 +189,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
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setOperationAction(ISD::LOAD, MVT::i64, Promote);
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AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
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setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
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AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
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18
test/CodeGen/R600/misaligned-load.ll
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18
test/CodeGen/R600/misaligned-load.ll
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@ -0,0 +1,18 @@
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; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI: @byte_aligned_load64
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: s_endpgm
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define void @byte_aligned_load64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) {
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entry:
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%0 = load i64 addrspace(3)* %in, align 1
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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