6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-21 18:29:46 +00:00
Code Issues Projects Releases Wiki Activity

[AArch64][NEON] Added SXTL and SXTL2 instruction aliases

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198437 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ana Pazos 2014-01-03 19:20:31 +00:00
parent d329ef5a3c
commit 5124fef085
2 changed files with 43 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
lib/Target/AArch64/AArch64InstrNEON.td
View File

@ -1775,6 +1775,23 @@ multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
// Signed integer lengthen (vector) is alias for SSHLL Vd, Vn, #0
// Signed integer lengthen (vector, second part) is alias for SSHLL2 Vd, Vn, #0
// FIXME: This is actually the preferred syntax but TableGen can't deal with
// custom printing of aliases.
class NeonI_sxtl_alias<string asmop, string lane, string laneOp,
Instruction inst, RegisterOperand VPRC,
RegisterOperand VPRCOp>
: NeonInstAlias<asmop # "\t$Rd" # lane #", $Rn" # laneOp,
(inst VPRC:$Rd, VPRCOp:$Rn, 0), 0b0>;
def SXTLvv_8B : NeonI_sxtl_alias<"sxtl", ".8h", ".8b", SSHLLvvi_8B, VPR128, VPR64>;
def SXTLvv_4H : NeonI_sxtl_alias<"sxtl", ".4s", ".4h", SSHLLvvi_4H, VPR128, VPR64>;
def SXTLvv_2S : NeonI_sxtl_alias<"sxtl", ".2d", ".2s", SSHLLvvi_2S, VPR128, VPR64>;
def SXTL2vv_16B : NeonI_sxtl_alias<"sxtl2", ".8h", ".16b", SSHLLvvi_16B, VPR128, VPR128>;
def SXTL2vv_8H : NeonI_sxtl_alias<"sxtl2", ".4s", ".8h", SSHLLvvi_8H, VPR128, VPR128>;
def SXTL2vv_4S : NeonI_sxtl_alias<"sxtl2", ".2d", ".4s", SSHLLvvi_4S, VPR128, VPR128>;
// Rounding/Saturating shift
class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
RegisterOperand VPRC, ValueType Ty, Operand ImmTy,

26
test/MC/AArch64/neon-sxtl.s Normal file
View File

@ -0,0 +1,26 @@
// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
// Check that the assembler can handle the documented syntax for AArch64
//------------------------------------------------------------------------------
// Signed integer lengthen (vector)
//------------------------------------------------------------------------------
sxtl v0.8h, v1.8b
sxtl v0.4s, v1.4h
sxtl v0.2d, v1.2s
// CHECK: sshll v0.8h, v1.8b, #0 // encoding: [0x20,0xa4,0x08,0x0f]
// CHECK: sshll v0.4s, v1.4h, #0 // encoding: [0x20,0xa4,0x10,0x0f]
// CHECK: sshll v0.2d, v1.2s, #0 // encoding: [0x20,0xa4,0x20,0x0f]
//------------------------------------------------------------------------------
// Signed integer lengthen (vector, second part)
//------------------------------------------------------------------------------
sxtl2 v0.8h, v1.16b
sxtl2 v0.4s, v1.8h
sxtl2 v0.2d, v1.4s
// CHECK: sshll2 v0.8h, v1.16b, #0 // encoding: [0x20,0xa4,0x08,0x4f]
// CHECK: sshll2 v0.4s, v1.8h, #0 // encoding: [0x20,0xa4,0x10,0x4f]
// CHECK: sshll2 v0.2d, v1.4s, #0 // encoding: [0x20,0xa4,0x20,0x4f]