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[SystemZ] Rename 32-bit GPR registers
I'm about to add support for high-word operations, so it seemed better for the low-word registers to have names like R0L rather than R0W. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191655 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -28,10 +28,10 @@
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using namespace llvm;
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using namespace llvm;
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const unsigned SystemZMC::GR32Regs[16] = {
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const unsigned SystemZMC::GR32Regs[16] = {
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SystemZ::R0W, SystemZ::R1W, SystemZ::R2W, SystemZ::R3W,
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SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
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SystemZ::R4W, SystemZ::R5W, SystemZ::R6W, SystemZ::R7W,
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SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
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SystemZ::R8W, SystemZ::R9W, SystemZ::R10W, SystemZ::R11W,
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SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
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SystemZ::R12W, SystemZ::R13W, SystemZ::R14W, SystemZ::R15W
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SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
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};
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};
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const unsigned SystemZMC::GR64Regs[16] = {
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const unsigned SystemZMC::GR64Regs[16] = {
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@ -23,7 +23,7 @@ def RetCC_SystemZ : CallingConv<[
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// call-clobbered argument registers available for code that doesn't
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// call-clobbered argument registers available for code that doesn't
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// care about the ABI. (R6 is an argument register too, but is
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// care about the ABI. (R6 is an argument register too, but is
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// call-saved and therefore not suitable for return values.)
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// call-saved and therefore not suitable for return values.)
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CCIfType<[i32], CCAssignToReg<[R2W, R3W, R4W, R5W]>>,
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CCIfType<[i32], CCAssignToReg<[R2L, R3L, R4L, R5L]>>,
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>,
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>,
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// ABI-complaint code returns float and double in F0. Make the
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// ABI-complaint code returns float and double in F0. Make the
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@ -53,7 +53,7 @@ def CC_SystemZ : CallingConv<[
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// The first 5 integer arguments are passed in R2-R6. Note that R6
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// The first 5 integer arguments are passed in R2-R6. Note that R6
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// is call-saved.
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// is call-saved.
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CCIfType<[i32], CCAssignToReg<[R2W, R3W, R4W, R5W, R6W]>>,
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CCIfType<[i32], CCAssignToReg<[R2L, R3L, R4L, R5L, R6L]>>,
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
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CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
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// The first 4 float and double arguments are passed in even registers F0-F6.
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// The first 4 float and double arguments are passed in even registers F0-F6.
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@ -733,7 +733,7 @@ static bool canUseSiblingCall(CCState ArgCCInfo,
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if (!VA.isRegLoc())
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if (!VA.isRegLoc())
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return false;
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return false;
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unsigned Reg = VA.getLocReg();
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unsigned Reg = VA.getLocReg();
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if (Reg == SystemZ::R6W || Reg == SystemZ::R6D)
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if (Reg == SystemZ::R6L || Reg == SystemZ::R6D)
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return false;
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return false;
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}
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}
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return true;
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return true;
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@ -2834,12 +2834,12 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
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// LoopMBB:
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// LoopMBB:
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// %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
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// %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
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// %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
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// %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
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// R0W = %CharReg
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// R0L = %CharReg
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// %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0W
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// %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
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// JO LoopMBB
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// JO LoopMBB
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// # fall through to DoneMMB
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// # fall through to DoneMMB
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//
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//
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// The load of R0W can be hoisted by post-RA LICM.
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// The load of R0L can be hoisted by post-RA LICM.
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MBB = LoopMBB;
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MBB = LoopMBB;
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BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
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BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
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@ -2848,7 +2848,7 @@ SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
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BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
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BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
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.addReg(Start2Reg).addMBB(StartMBB)
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.addReg(Start2Reg).addMBB(StartMBB)
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.addReg(End2Reg).addMBB(LoopMBB);
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.addReg(End2Reg).addMBB(LoopMBB);
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BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0W).addReg(CharReg);
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BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
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BuildMI(MBB, DL, TII->get(Opcode))
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BuildMI(MBB, DL, TII->get(Opcode))
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.addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
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.addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
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.addReg(This1Reg).addReg(This2Reg);
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.addReg(This1Reg).addReg(This2Reg);
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@ -361,7 +361,7 @@ let mayLoad = 1, mayStore = 1 in
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defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
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defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
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// String moves.
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// String moves.
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let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0W] in
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let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
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defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
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defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -1023,7 +1023,7 @@ let mayLoad = 1, Defs = [CC] in
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defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
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defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
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// String comparison.
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// String comparison.
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let mayLoad = 1, Defs = [CC], Uses = [R0W] in
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let mayLoad = 1, Defs = [CC], Uses = [R0L] in
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defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
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defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
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// Test under mask.
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// Test under mask.
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@ -1198,7 +1198,7 @@ let usesCustomInserter = 1 in {
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}
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}
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// Search a block of memory for a character.
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// Search a block of memory for a character.
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let mayLoad = 1, Defs = [CC], Uses = [R0W] in
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let mayLoad = 1, Defs = [CC], Uses = [R0L] in
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defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
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defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -42,13 +42,13 @@ SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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if (TFI->hasFP(MF)) {
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if (TFI->hasFP(MF)) {
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// R11D is the frame pointer. Reserve all aliases.
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// R11D is the frame pointer. Reserve all aliases.
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11D);
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Reserved.set(SystemZ::R11W);
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Reserved.set(SystemZ::R11L);
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Reserved.set(SystemZ::R10Q);
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Reserved.set(SystemZ::R10Q);
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}
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}
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// R15D is the stack pointer. Reserve all aliases.
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// R15D is the stack pointer. Reserve all aliases.
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R15D);
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Reserved.set(SystemZ::R15W);
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Reserved.set(SystemZ::R15L);
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Reserved.set(SystemZ::R14Q);
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Reserved.set(SystemZ::R14Q);
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return Reserved;
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return Reserved;
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}
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}
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@ -70,8 +70,8 @@ class GPR128<bits<16> num, string n, GPR64 high, GPR64 low>
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// General-purpose registers
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// General-purpose registers
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foreach I = 0-15 in {
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foreach I = 0-15 in {
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def R#I#W : GPR32<I, "r"#I>;
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def R#I#L : GPR32<I, "r"#I>;
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def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"W")>, DwarfRegNum<[I]>;
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def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L")>, DwarfRegNum<[I]>;
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}
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}
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foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
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foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
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@ -81,8 +81,8 @@ foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
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/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
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/// Allocate the callee-saved R6-R13 backwards. That way they can be saved
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/// together with R14 and R15 in one prolog instruction.
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/// together with R14 and R15 in one prolog instruction.
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defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uW", 0, 5),
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defm GR32 : SystemZRegClass<"GR32", i32, 32, (add (sequence "R%uL", 0, 5),
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(sequence "R%uW", 15, 6))>;
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(sequence "R%uL", 15, 6))>;
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defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5),
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defm GR64 : SystemZRegClass<"GR64", i64, 64, (add (sequence "R%uD", 0, 5),
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(sequence "R%uD", 15, 6))>;
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(sequence "R%uD", 15, 6))>;
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